EDD5104ABTA-6B ELPIDA [Elpida Memory], EDD5104ABTA-6B Datasheet
EDD5104ABTA-6B
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EDD5104ABTA-6B Summary of contents
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... PRELIMINARY DATA SHEET 512M bits DDR SDRAM EDD5104ABTA (128M words 4 bits) EDD5108ABTA (64M words 8 bits) Description The EDD5104AB is a 512M bits Double Data Rate (DDR) SDRAM organized as 33,554,432 words 4 banks. The EDD5108AB is a 512M bits DDR SDRAM organized as 16,777,216 words banks. Read and write operations are performed at the cross points of the CK and the /CK ...
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... Ordering Information Mask Organization Part number version (words EDD5104ABTA-6B EDD5104ABTA-7A B 128M EDD5104ABTA-7B EDD5108ABTA-6B EDD5108ABTA-7A 64M 8 EDD5108ABTA-7B Part Number Elpida Memory Type D: Monolithic Device Product Code D: DDR SDRAM Density / Bank 51: 512M / 4 banks Bit Organization Voltage, Interface A: 2 ...
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... CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Electrical Specifications.................................................................................................................................4 Block Diagram .............................................................................................................................................10 Pin Function.................................................................................................................................................11 Command Operation ...................................................................................................................................13 Simplified State Diagram .............................................................................................................................21 Operation of the DDR SDRAM ....................................................................................................................22 Timing Waveforms.......................................................................................................................................41 Package Drawing ........................................................................................................................................47 Recommended Soldering Conditions ..........................................................................................................48 Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA 3 ...
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... VIN (DC) specifies the allowable dc execution of each differential input. 5. VID (DC) specifies the input differential voltage required for switching. 6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Symbol Rating VT –1.0 to +3.6 VDD – ...
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... Input leakage current IL –2 Output leakage current IOZ –5 Output high current IOH –15.2 Output low current IOL 15.2 Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA max Unit Test condition 150 150 CKE ≥ VIH, mA 135 135 tRC = tRC (min.) CKE ≥ VIH ...
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... DQS falling edge to CK setup time tDSS DQS falling edge hold time from CK tDSH DQS input high pulse width tDQSH 0.35 DQS input low pulse width tDQSL Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Pins min. Typ CK, /CK 2.0 — All other input pins 2.0 — ...
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... For each of the terms above, if not already an integer, round to the next highest integer. Example: For –7A Speed 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA -6B -7A max. min. ...
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... Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate CK VID /CK Measurement point Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Symbol Value VREF VDDQ/2 VTT VREF VIH (AC) VREF 0.31 VIL (AC) VREF ...
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... DM to data in latency Mode register set command cycle time Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Number of clock cycle 6ns Symbol min. max. tWPD ...
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... Block Diagram CK /CK CKE A0 to A12, BA0, BA1 Mode register /CS /RAS /CAS /WE Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit ...
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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Column address AY0 to AY9, AY11, AY12 AY0 to AY9, AY11, BA1 ...
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... DQS (input and output pin): DQS provides the read data strobe (as output) and the write data strobe (as input). VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA 12 ...
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... This command starts a write operation. The start address of the burst write is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA CKE Symbol n – ...
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... Power down exit (PDEX) Remark: H: VIH. L: VIL. : VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA BA1 CKE n – 1 ...
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... Refresh H 3 (auto-refresh Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Address Command Operation DESL NOP NOP NOP BST ILLEGAL* BA, CA, A10 READ/READA ILLEGAL* BA, CA, A10 WRIT/WRITA ILLEGAL* BA, RA ACT ILLEGAL* BA, A10 PRE, PALL NOP ...
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... Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Address Command Operation DESL NOP NOP NOP BST ILLEGAL* BA, CA, A10 READ/READA ILLEGAL* BA, CA, A10 WRIT/WRITA ILLEGAL* BA, RA ACT ILLEGAL* BA, A10 PRE, PALL ILLEGAL* ...
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... Remark: H: VIH. L: VIL. : VIH or VIL Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Address Command Operation DESL NOP NOP NOP BST ILLEGAL BA, CA, A10 READ/READA ILLEGAL* BA, CA, A10 WRIT/WRITA ILLEGAL* BA, RA ACT ILLEGAL* BA, A10 ...
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... Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. EDD5104ABTA and EDD5108ABTA support the concurrent auto-precharge feature, a read with auto- precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply ...
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... Remark: H: VIH. L: VIL. : VIH or VIL Note: Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Operation INVALID, CK (n-1) would exit self refresh Self refresh recovery ...
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... DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA 20 ...
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... POWER APPLIED ON PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO ...
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... BA1 A12 A11 A10 MRS CAS Latency A8 DLL Reset Yes Mode Register Set [MRS] (BA0 = 0, BA1 = 0) Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA PALL REF REF REF RFC 200 cycles (min ...
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... Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Burst length = 4 Starting Ad. Addressing(decimal) Interleave A1 A0 Sequence ...
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... Command NOP ACT NOP Address Row DQS Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) ...
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... DQS is referred as write postamble /CK tRCD Command NOP ACT NOP Row Address DQS Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA t1 t1.5 t2 t2.5 t3 t3.5 NOP tAC,tDQSCK out0 out1 out2 out3 tRPRE tAC,tDQSCK out0 out1 out2 Read Operation (/CAS Latency ...
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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK READ Command DQS DQS CL = 2.5 DQ Burst Stop during a Read Operation Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA t1 t1.5 t2 t2.5 t3 t3.5 t4 BST NOP tBSTZ 2 cycles out0 out1 tBSTZ 2.5 cycles ...
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... CK /CK tRAS (min) tRCD (min) ACT NOP WRITA Command DM DQS DQ Note: Internal auto-precharge starts at the timing indicated by " Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA tRPD 2 cycles (= BL/2) READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP BL cycles in1 in2 ...
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... Bank0 Active READ to READ Command Interval (same ROW address in the same bank) Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Operation The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘ ...
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... CK /CK Command ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active READ to READ Command Interval (different bank) Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA READ READ NOP Column A Column B out out A0 A1 Column = A Column = B Read Read ...
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... Bank0 Active WRITE to WRITE Command Interval (same ROW address in the same bank) Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Operation The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...
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... ACT NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 31 ...
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... DQ High-Z DQS OUTPUT Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Operation Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...
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... DQS Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Operation To complete the burst operation, the consecutive read command should be performed tWRD (= BL after the write command. ...
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... DQS Data masked [WRITE to READ delay = 1 clock cycle] Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. ...
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... DM DQ in0 in1 DQS Data masked Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 3 clock cycle] Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA NOP CL=2 in2 in3 out0 out1 out2 out3 ...
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... READ to PRECHARGE Command Interval (same bank): To output all data ( CLK /CLK Command NOP NOP READ DQ DQS tRPD = BL/2 READ to PRECHARGE Command Interval (same bank): To output all data ( Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA PRE/ NOP PALL out0 out1 out2 out3 PRE/ NOP ...
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... READ to PRECHARGE Command Interval (same bank): To stop output data ( /CK Command NOP READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA NOP PRE/PALL out0 out1 tHZP ...
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... In order to write the last input data, tWR (min) must be satisfied. When the precharge command is issued, the invalid data must be masked by DM /CK Command WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA PRE/PALL NOP tWPD tWR in2 in3 Last data input ...
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... Address CODE Mode Register Set Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued ...
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... DM can mask input data. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS DQ DM Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Mask Mask Write mask latency = 0 DM Control ...
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... DQS tLZ DQ (Dout) Write Timing Definition tCK /CK CK tDQSS DQS tWPRES tWPRE DQ (Din) tDS DM tDS Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tDQSQ tQH tAC tAC tAC tDQSQ tQH tQH tDSS tDSH ...
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... A10 tIS tIH Address DM High-Z DQS High-Z DQ (output) Bank 0 Bank 0 Active Active Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA tRC tRAS tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...
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... A10 tIS tIH tIS tIH Address DQS (input (input) Bank 0 Bank 0 Bank 0 Active Active Write Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDH tDS tDS tDH tWR tDH 43 tRP tIS tIH ...
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... Read/Write Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address R:a C:a DM DQS DQ (output) High-Z DQ (input) Bank 0 Bank 0 Active Read Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA tMRD Bank 3 Bank 3 Read Active R:b C tRWD ...
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... Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA R: b High-Z tRFC Auto Bank 0 Refresh Active Bank 0 Read VIH or VIL ...
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... CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active Bank 0 Read VIH or VIL ...
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... 0.91 max. 0. Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA Unit: mm 0.80 Nom 0.25 0.60 ± 0.15 ECA-TS2-0029-01 ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD51XXABTA. Type of Surface Mount Device EDD51XXABTA: 66-pin Plastic TSOP (II) 10.16mm(400) Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA 48 ...
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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA 49 CME0107 ...
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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E0237E30 (Ver. 3.0) EDD5104ABTA, EDD5108ABTA 50 M01E0107 ...