EDD5104ABTA-6B ELPIDA [Elpida Memory], EDD5104ABTA-6B Datasheet - Page 9

• Manufacturer Part Number: EDD5104ABTA-6B
• Description: 512M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Timing Parameter Measured in Clock Cycle
tCK
Parameter
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
Write to read command delay (to input all data)
Burst stop command to write command delay
(CL = 2)
(CL = 2.5)
Burst stop command to DQ High-Z
(CL = 2)
(CL = 2.5)
Read command to write command delay
(to output all data)
(CL = 2)
(CL = 2.5)
Pre-charge command to High-Z
(CL = 2)
(CL = 2.5)
Write command to data in latency
Write recovery time
DM to data in latency
Mode register set command cycle time
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
Power down exit to command input
Preliminary Data Sheet E0237E30 (Ver. 3.0)
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
tRWD
tRWD
tHZP
tHZP
tWCD
tWR
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
9
EDD5104ABTA, EDD5108ABTA
Number of clock cycle
6ns
min.
4 + BL/2
BL/2
2 + BL/2
2
3
2
2.5
2 + BL/2
3 + BL/2
2
2.5
1
3
0
2
12
200
1
1
max.
2
2.5
2
2.5
1
0
1
7.5ns
min.
3 + BL/2
BL/2
2 + BL/2
2
3
2
2.5
2 + BL/2
3 + BL/2
2
2.5
1
2
0
2
10
200
1
1
max.
2
2.5
2
2.5
1
0
1