EDD5108AFTA_06 ELPIDA [Elpida Memory], EDD5108AFTA_06 Datasheet

EDD5108AFTA_06

Manufacturer Part Number

EDD5108AFTA_06

Description

512M bits DDR SDRAM

Manufacturer

ELPIDA [Elpida Memory]

Datasheet

1.EDD5108AFTA_06.pdf (52 pages)

Current page: 1 of 52
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Specifications

• Density: 512M bits

• Organization

⎯ 16M words × 8 bits × 4 banks (EDD5108AFTA)

⎯ 8M words × 16 bits × 4 banks (EDD5116AFTA)

• Package: 66-pin plastic TSOP (II)

⎯ Lead-free (RoHS compliant)

• Power supply:

⎯ DDR400:

⎯ DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V

• Data rate: 400Mbps/333Mbps/266Mbps (max.)

• Four internal banks for concurrent operation

• Interface: SSTL_2

• Burst lengths (BL): 2, 4, 8

• Burst type (BT):

⎯ Sequential (2, 4, 8)

⎯ Interleave (2, 4, 8)

• /CAS Latency (CL): 2, 2.5, 3

• Precharge: auto precharge option for each burst

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

⎯ Average refresh period: 7.8μs

• Operating ambient temperature range

⎯ TA = 0°C to +70°C

Document No. E0699E50 (Ver. 5.0)

Date Published November 2006 (K) Japan

Printed in Japan

URL: http://www.elpida.com

access

VDD, VDDQ = 2.6V ± 0.1V

EDD5116AFTA (32M words × 16 bits)

EDD5108AFTA (64M words × 8 bits)

512M bits DDR SDRAM

DATA SHEET

Features

• Double-data-rate architecture; two data transfers per

• The high-speed data transfer is realized by the 2 bits

• Bi-directional data strobe (DQS) is transmitted

• Data inputs, outputs, and DM are synchronized with

• DQS is edge-aligned with data for READs; center-

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

• Commands entered on each positive CK edge; data

• Data mask (DM) for write data

clock cycle

prefetch pipelined architecture

/received with data for capturing data at the receiver

DQS

aligned with data for WRITEs

transitions

and data mask referenced to both edges of DQS

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