EDD5108AFTA_06 ELPIDA [Elpida Memory], EDD5108AFTA_06 Datasheet - Page 35

• Manufacturer Part Number: EDD5108AFTA_06
• Description: 512M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

A Read command to the consecutive Write command interval with the BST command
1. Same
2. Same
3. Different
Data Sheet E0699E50 (Ver. 5.0)
Command
Destination row of the consecutive write
command
Bank
address
DQS
/CK
DM
DQ
CK
Row address State
Same
Different
Any
READ
High-Z
t0
BST
ACTIVE
—
ACTIVE
IDLE
t1
tBSTW (≥ tBSTZ)
READ to WRITE Command Interval
t2
tBSTZ (= CL)
Operation
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
NOP
OUTPUT
t3
out0 out1
35
WRIT
t4
EDD5108AFTA, EDD5116AFTA
in0
t5
in1
in2
INPUT
t6
NOP
in3
t7
BL = 4
CL = 3
t8