HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 73

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HT68F14

Manufacturer Part Number
HT68F14
Description
Enhanced I/O Flash Type MCU
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet

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Part Number
Manufacturer
Quantity
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Company:
Part Number:
HT68F14
Quantity:
310
Note:
Rev. 1.10
Period
Period
CCRP
CCRP
Duty
Duty
1. Here TnDPX=0 -- Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
TM O/P Pin
TM O/P Pin
Flag TnAF
Flag TnPF
CCRA Int.
CCRP Int.
TnPAU
TnPOL
CCRP
CCRA
TnON
Counter Value
(TnOC=1)
(TnOC=0)
PWM Duty Cycle
set by CCRA
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to
select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is
used to reverse the polarity of the PWM output waveform.
001b
001b
128
128
CTM, PWM Mode, Edge-aligned Mode, T0DPX=0
If f
The CTM PWM output frequency = (f
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
CTM, PWM Mode, Edge-aligned Mode, T0DPX=1
The PWM output period is determined by the CCRA register value together with the TM clock while
the PWM duty cycle is defined by the CCRP register value.
SYS
= 16MHz, TM clock source is f
010b
010b
256
256
Counter cleared
011b
011b
by CCRP
384
384
PWM Mode -- TnDPX = 0
SYS
100b
100b
512
512
SYS
73
PWM Period
set by CCRP
/4) / 512 = f
Enhanced I/O Flash Type MCU
/4, CCRP = 100b and CCRA =128,
CCRA
CCRA
Pause Resume
HT68F13/HT68F14/HT68F15
101b
101b
640
640
SYS
/2048 = 7.8125 kHz, duty = 128/512 = 25%.
Output controlled by
other pin-shared function
TnDPX = 0; TnM [1:0] = 10
Counter Stop if
TnON bit low
110b
110b
768
768
PWM resumes
operation
Counter Reset when
TnON returns high
Output Inverts
when TnPOL = 1
111b
111b
896
896
February 9, 2011
Time
000b
1024
000b
1024

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