HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 82

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Rev. 1.10
Period
Period
CCRP
CCRP
Duty
Duty
PWM Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The
PWM function within the TM is useful for applications which require functions such as motor control,
heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty
cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent
DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM
operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while the
other one is used to control the duty cycle. Which register is used to control either frequency or duty
cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and
duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to
select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is
used to reverse the polarity of the PWM output waveform.
001b
001b
128
128
STM, PWM Mode, Edge-aligned Mode, T0DPX=0
If f
The STM PWM output frequency = (f
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
STM, PWM Mode, Edge-aligned Mode, T0DPX=1
The PWM output period is determined by the CCRA register value together with the TM clock while
the PWM duty cycle is defined by the CCRP register value.
SYS
= 16MHz, TM clock source is f
010b
010b
256
256
011b
011b
384
384
SYS
100b
100b
512
512
SYS
82
/4) / 512 = f
/4, CCRP = 100b and CCRA =128,
CCRA
CCRA
101b
101b
640
640
SYS
/2048 = 7.8125 kHz, duty = 128/512 = 25%.
110b
110b
768
768
111b
111b
896
896
February 9, 2011
000b
1024
000b
1024