EX256-CS100 ACTEL [Actel Corporation], EX256-CS100 Datasheet - Page 24

• Manufacturer Part Number: EX256-CS100
• Description: eX Automotive Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Timing Characteristics
Timing characteristics for eX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer tool in the Designer software or performing
simulation with post-layout delays.
Table 1-17
characteristics for automotive eX devices.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to six percent of the nets in a design may be designated
as critical.
Temperature and Voltage Derating Factors
Table 1-16 • Temperature and Voltage Derating Factors
1 -2 0
eX Automotive Family FPGAs
V
2.3
2.5
2.7
CCA
(Normalized to Worst-Case Commercial, T
on
page 1-21
The
0.70
0.65
0.61
–55
input
lists
and
0.70
0.66
0.62
–40
sample
output
timing
buffer
0.77
0.72
0.67
J
0
= 125°C, V
Junction Temperature (T
v3.2
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, no more than six
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to
8.4 ns delay. This additional delay is represented
statistically in higher fanout routing delays.
Timing Derating
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum
processing.
minimum
temperature, and worst-case processing.
CCA
0.78
0.73
0.69
25
= 2.3 V)
operating
operating
Maximum
J
0.88
0.83
0.78
)
70
voltage,
temperature,
timing
0.91
0.85
0.80
85
maximum
parameters
and
operating
best-case
125
1.00
0.93
0.88
reflect