EX256-CS100 ACTEL [Actel Corporation], EX256-CS100 Datasheet - Page 26

• Manufacturer Part Number: EX256-CS100
• Description: eX Automotive Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Table 1-17 • eX Family Timing Characteristics
1 -2 2
Parameter
t
t
t
Dedicated (Hardwired) Array Clock Networks
t
t
t
t
t
t
f
Routed Array Clock Networks
t
t
t
t
t
t
t
t
t
t
t
2.5 V LVCMOS2 Output Module Timing
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
IRD4
IRD8
IRD12
HCKH
HCKL
HPWH
HPWL
HCKSW
HP
HMAX
RCKH
RCKL
RCKH
RCKL
RCKH
RCKL
RPWH
RPWL
RCKSW
RCKSW
RCKSW
DLH
DHL
DHLS
eX Automotive Family FPGAs
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
3
3
3
(Worst-Case Automotive Conditions, V
Description
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
Input Low to High
(Pad to R-Cell Input)
Input High to Low
(Pad to R-Cell Input)
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Minimum Period
Maximum Frequency
Input Low to High (Light Load)
(Pad to R-Cell Input)
Input High to Low (Light Load)
(Pad to R-Cell Input)
Input Low to High (50% Load)
(Pad to R-Cell Input)
Input High to Low (50% Load)
(Pad to R-Cell Input)
Input Low to High (100% Load)
(Pad to R-Cell Input)
Input High to Low (100% Load)
(Pad to R-Cell Input)
Min. Pulse Width High
Min. Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—Low Slew
PD
+ t
RD1
+ t
4
PDn
(V
, t
CCI
RCO
= 2.3 V)
CCA
+ t
RD1
= 2.3 V, T
+ t
v3.2
PDn
or t
J
= 125°C)
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Min.
2.0
2.0
4.0
2.0
2.0
‘Std.’ Speed
Max.
20.8
250
6.3
1.1
1.9
2.8
1.8
1.8
0.1
1.6
1.6
1.9
1.9
2.3
2.3
0.3
0.2
0.1
5.9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns