K6X1008C2D-BF55T00 Samsung, K6X1008C2D-BF55T00 Datasheet - Page 8

• Manufacturer Part Number: K6X1008C2D-BF55T00
• Description: power, ram, low, Memory, Semiconductors and Actives, bit, cmos
• Manufacturer: Samsung

DATA RETENTION WAVE FORM
K6X1008C2D Family
CS
CS
TIMING WAVEFORM OF WRITE CYCLE(3)
1
Address
CS
CS
WE
Data in
Data out
V
4.5V
2.2V
V
CS
GND
2
V
4.5V
CS
V
0.4V
GND
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
2. t
3. t
4. t
CC
DR
CC
DR
controlled
controlled
CS
t
in case a write ends as CS
CW
AS
WR
WP
1
2
1
2
2
is measured from the address valid to the beginning of write.
is measured from the begining of write to the end of write.
is measured from the CS
is measured from the end of write to the address change. t
going high and WE going low: A write end at the earliest transition among CS
2
going to low.
1
going low or CS
High-Z
t
SDR
t
t
SDR
AS(3)
1
, a high CS
2
going high to the end of write.
(CS
2
Controlled)
2
and a low WE. A write begins at the latest transition among CS
Data Retention Mode
WR
Data Retention Mode
8
t
applied in case a write ends as CS
AW
CS≥V
t
t
WC
CS
t
CW(2)
CW(2)
2
CC
≤0.2V
t
WP(1)
- 0.2V
1
t
DW
going high, CS
Data Valid
t
WR(4)
t
DH
2
1
going low and WE going high,
or WE going high t
t
RDR
High-Z
t
RDR
CMOS SRAM
WR2
1
goes low,
Revision 3.0
applied
March 2005