GS88237BB-200IV GSI Technology, GS88237BB-200IV Datasheet

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GS88237BB-200IV

Manufacturer Part Number
GS88237BB-200IV
Description
256k X 36 9mb Scd/dcd Sync Burst Sram
Manufacturer
GSI Technology
Datasheet
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump and 165-bump BGA packages
• RoHS-compliant 119-bump and 165-bump BGA packages
Functional Description
Applications
The GS88237BB/D-xxxV is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
Rev: 1.04 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
available
9Mb SCD/DCD Sync Burst SRAM
Pipeline
3-1-1-1
Parameter Synopsis
Curr
1/28
256K x 36
tCycle
t
KQ
(x36)
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
SCD and DCD Pipelined Reads
The GS88237BB/D-xxxV is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS88237BB/D-xxxV operates on a 1.8 V or 2.5 V power
supply. All inputs are 1.8 V or 2.5 V compatible. Separate output
power (V
internal circuits and are 1.8 V or 2.5 V compatible.
-250
330
2.5
4.0
DDQ
-200
270
2.5
5.0
) pins are used to decouple output noise from the
Unit
mA
ns
ns
GS88237BB/D-xxxV
© 2003, GSI Technology
250 MHz–200 MHz
1.8 V or 2.5 V V
1.8 V or 2.5 V I/O
DD

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GS88237BB-200IV Summary of contents

Page 1

... Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS88237BB/D-xxxV operates 2.5 V power supply. All inputs are 1 2.5 V compatible. Separate output power (V DDQ internal circuits and are 1 ...

Page 2

... DQP DDQ NC A LBO V DD DNU TMS TDI TCK TDO DDQ 2/28 GS88237BB/D-xxxV DDQ DQP DDQ ...

Page 3

... TDI A1 TDO A A TMS A0 TCK A 3/28 GS88237BB/D-xxxV (Package ADV ADSP DQB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB ...

Page 4

... GS88237BB/D-xxxV BGA Pin Description Symbol Type I — NC — ADV I ADSC, ADSP LBO FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low ...

Page 5

... Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 1.04 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237BB/D-xxxV Block Diagram Counter Load Register D Q Register D ...

Page 6

... Note: The burst counter wraps to initial state on the 5th clock. 6/28 GS88237BB/D-xxxV Function Linear Burst Interleaved Burst Active Standby Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance) ...

Page 7

... may be used in any combination with BW to write single or multiple bytes. D 7/28 GS88237BB/D-xxxV B B Notes ...

Page 8

... Key None X H External R L External R L External W L Next CR X Next CR H Next CW X Next CW H Current X Current H Current X Current H 8/28 GS88237BB/D-xxxV 3 ADSP ADSC ADV ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 9/28 GS88237BB/D-xxxV First Read Burst Read BW, and GW) control inputs, and ...

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 10/28 GS88237BB/D-xxxV First Read Burst Read CR © 2003, GSI Technology ...

Page 11

... V 2.3 DD2 V 1.7 DDQ1 V 2.3 DDQ2 +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Symbol Min. V 0.6 11/28 GS88237BB/D-xxxV Value –0.5 to 4.6 –0 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 1 ...

Page 12

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Overshoot Measurement and Timing Symbol Test conditions I/O OUT 12/28 GS88237BB/D-xxxV 0.3*V — Typ. Max. Unit ° ° 20% tKC DD IL Typ. Max. Unit 4 5 ...

Page 13

... –4 mA, V OH1 –8 mA, V OH2 OH DDQ OL1 OL2 OL 13/28 GS88237BB/D-xxxV Figure 1 Output Load 1 * 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance Min – ≥ –100 –1 uA OUT DD Min = 1 – 0.4 V ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Mode Symbol I DD (x36) Pipeline I DDQ I — Pipeline SB I Pipeline — DD and V operation. DD3 DDQ 14/28 GS88237BB/D-xxxV -250 -200 0 –40 0 –40 to 70°C to 85°C to 70°C to 85°C 290 300 240 250 ...

Page 15

... GS88237BB/D-xxxV -200 Unit Min Max 5.0 ns — 2.5 ns — 1.0 — ns 1.0 ns — 1.4 ns — 0.4 ns — — 2.5 ns 2.5 ns — 1.3 — ns 1.7 ns — 1.0 2.5 ...

Page 16

... Pipeline Mode Timing (+1) Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKC tKC tKH tKH tKL tKL ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH Q(A) D(B) 16/28 GS88237BB/D-xxxV Deselect Deselected with E1 tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2003, GSI Technology ...

Page 17

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 17/28 GS88237BB/D-xxxV 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2003, GSI Technology ...

Page 18

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.04 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description 18/28 GS88237BB/D-xxxV © 2003, GSI Technology ...

Page 19

... Control Signals Test Access Port (TAP) Controller Not Used 19/28 GS88237BB/D-xxxV · · · TDO GSI Technology JEDEC Vendor ID Code © 2003, GSI Technology 0 1 ...

Page 20

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 20/28 GS88237BB/D-xxxV 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2003, GSI Technology ...

Page 21

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.04 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 21/28 GS88237BB/D-xxxV © 2003, GSI Technology ...

Page 22

... Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.04 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description 22/28 GS88237BB/D-xxxV Notes ...

Page 23

... OLJ V V OHJC V OLJC +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. DDn supply. DDQ Conditions V – DDQ V /2 DDQ 23/28 GS88237BB/D-xxxV Min. Max. Unit Notes 0 –0.3 V DD1 0 –0.3 DD2 0 +0.3 V DD1 DD1 0 +0.3 V DD2 DD2 – ...

Page 24

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — — — ns — 24/28 GS88237BB/D-xxxV tTKL tTKL © 2003, GSI Technology ...

Page 25

... Rev: 1.04 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) 25/28 GS88237BB/D-xxxV ) 1.27 © 2003, GSI Technology ...

Page 26

... Rev: 1.04 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 26/28 GS88237BB/D-xxxV A1 CORNER 1.0 ...

Page 27

... GS88237BGD-250IV S/DCD Pipeline 256K x 36 GS88237BGD-200IV S/DCD Pipeline Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88237BB-200IVT. 2. This part is a Pipeline mode-only part Commercial Temperature Range ...

Page 28

... Updated mechanical drawing and added variation number to Content ordering information • Added 165 BGA Content • Added Pb-Free information • Updated entire datasheet to reflect different ordering Content information, speed bin offering, and AC characteristics 28/28 GS88237BB/D-xxxV Page;Revisions;Reason © 2003, GSI Technology ...

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