GS88237BB-200IV GSI Technology, GS88237BB-200IV Datasheet - Page 6

• Manufacturer Part Number: GS88237BB-200IV
• Description: 256k X 36 9mb Scd/dcd Sync Burst Sram
• Manufacturer: GSI Technology

Mode Pin Functions
Note:
There are pull-up devices on the ZQ and SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.04 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
1st address
4th address
FLXDrive Output Impedance Control
Single/Dual Cycle Deselect Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
00
11
10
11
00
01
00
01
10
11
Pin Name
6/28
SCD
LBO
ZQ
ZZ
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
3rd address
4th address
1st address
H or NC
H or NC
L or NC
State
H
H
L
L
L
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
High Drive (Low Impedance)
Low Drive (High Impedance)
Single Cycle Deselect
Dual Cycle Deselect
01
00
11
10
Standby, I
Interleaved Burst
Linear Burst
Function
Active
GS88237BB/D-xxxV
10
00
01
11
DD
© 2003, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18