ST72C334J4TAE STMicroelectronics, ST72C334J4TAE Datasheet - Page 38

• Manufacturer Part Number: ST72C334J4TAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces
• Manufacturer: STMicroelectronics

ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
POWER SAVING MODES (Cont’d)
10.4 ACTIVE HALT AND HALT MODES
Active Halt and Halt modes are the two lowest
power consumption modes of the MCU. They are
both entered by executing the HALT instruction.
The decision to enter either in Active Halt or Halt
mode is given by the MCC/RTC interrupt enable
flag (OIE bit in MCCSR register).
10.4.1 Active Halt Mode
Active Halt mode is the lowest power consumption
mode of the MCU with a real-time clock available.
It is entered by executing the HALT instruction
when the OIE bit of the Main Clock Controller Sta-
tus register (MCCSR) is set (see
"MAIN CLOCK CONTROLLER WITH REAL-TIME
CLOCK TIMER (MCC/RTC)" on page 53
details on the MCCSR register).
The MCU can exit Active Halt mode on reception
of either an MCC/RTC interrupt, a specific inter-
rupt (see
page
mode by means of a RESET or an interrupt, a
4096 CPU cycle delay occurs. After the start up
delay, the CPU resumes operation by servicing
the interrupt or by fetching the reset vector which
woke it up (see
When entering Active Halt mode, the I bit in the CC
register is cleared to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
In Active Halt mode, only the main oscillator and
its associated counter (MCC/RTC) are running to
keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
The safeguard against staying locked in Active
Halt mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
38/150
MCCSR
OIE bit
0
1
35) or a RESET. When exiting Active Halt
Halt mode
Active Halt mode
Power Saving Mode entered when HALT
Table 6, “Interrupt Mapping,” on
Figure
instruction is executed
22).
Section 13.2
for more
Figure 21. Active Halt Timing Overview
Figure 22. Active Halt Mode Flowchart
Notes:
1. Peripheral clocked with an external clock source
can still be active.
2. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from Active Halt mode
(such as external interrupt). Refer to
terrupt Mapping,” on page 35
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
[MCCSR.OIE=1]
INSTRUCTION
HALT INSTRUCTION
RUN
N
(MCCSR.OIE=1)
HALT
INTERRUPT
ACTIVE
HALT
Y
4096 CPU CYCLE
INTERRUPT
2)
RESET
4096 CPU CLOCK CYCLE
DELAY
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BITS
N
for more details.
DELAY
RESET
Y
VECTOR
FETCH
Table 6, “In-
RUN
1)
1)
OFF
OFF
OFF
ON
ON
ON
X
ON
ON
ON
X
0
3)
3)