IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet
IS46TR16128A-15HBLA2
Specifications of IS46TR16128A-15HBLA2
Related parts for IS46TR16128A-15HBLA2
IS46TR16128A-15HBLA2 Summary of contents
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... Faster speed options are backward compatible to slower speed options. Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products ...
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... VDD A3 L VSS A5 M VDD A7 N VSS RESET# Note: NC balls have no internal connection. NC(A15) is one of NC pins and reserved for higher densities. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DQ0 DQS DQS# DQ4 RAS# CAS# WE# ...
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... A3 P VSS A5 R VDD A7 T VSS RESET# Note: NC balls have no internal connection. NC(A14) and NC(A15) are one of NC pins and reserved for higher densities. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DQU7 VSS DQU1 DMU DQL0 DQSL ...
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... DQSU#, DQSL, DQSL# TDQS, TDQS# Output NC Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Function Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. ...
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... Supply VREFDQ Supply VREFCA Supply ZQ Supply Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DQ Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage DQ Ground Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage Ground Reference voltage for DQ ...
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... Write Abbreviation Function ACT Active PRE Precharge PREA Precharge All MRS Mode Register Set REF Refresh ZQCL ZQ Calibration Long Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 MRS,MPR, Initialization Write Leveling ZQCL ZQCL ZQ ZQCS Idle Calibration ACT Active Activating ...
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... BA2, “High” to BA0 and BA1.) 8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 – BA2). Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... CKE is pulled “LOW” before RESET being de-asserted (min. time 10 ns). 2. Follow Power-up Initialization Sequence steps 2 to 11. 3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands shown as below. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Feature is disabled in the Mode Register prior and after an MRS command, the ODT Signal can be registered either LOW or HIGH before, during and after the MRS command. The mode registers are divided into various fields depending on the functionality and/or modes. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Table below. The burst length is defined by bits A0-A1. Burst length options include fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR (in ns) by tCK Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A ...
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... TDQS (Termination Data Strobe feature of X8 DDR3 SDRAM that provides additional termination resistance outputs that may be useful in some system configurations. The TDQS function is available in X8 DDR3 SDRAM only and must be disabled via the mode register A11=0 in MR1 for X16 configuration. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... For more details refer to “Extended Temperature Usage”. DDR3 SDRAMs support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Power down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The basic concept of the MPR is shown in Figure 2.3.5.1. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 A12 ...
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... The RESET function is supported during MPR enable mode. MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] MPR MPR-Loc don’t care ( See Table 13 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Memory Core (all banks precharged) MR3[A2] Register pre-defined DQ, DM, DQS, DQS# Figure 2.3.5.1 MPR Block Diagram Normal operation, no MPR transaction ...
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... NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. NOTE: Good reference for the example of MPR feature is the JEDEC standard No.93-3D, 4.10.4 Protocol example. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... IS43/46TR16128A, IS43/46TR16128AL, IS43/46TR82560A, IS43/46TR82560AL Relevant Timing Parameters AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD, and tMPRR. For more details refer to “Electrical Characteristics & AC Timing Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 19 ...
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... VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A ...
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... CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc). Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the skew between all DQ, DQS, and DQS# signals will still be tDQSQ Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A ...
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... IS43/46TR16128A, IS43/46TR16128AL, IS43/46TR82560A, IS43/46TR82560AL Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 23 ...
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... Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Once a don’t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be met. ...
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... NOTE: In Write Leveling Mode with its output buffer disabled (MR1[bit7 with MR1[bit12 all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit7 with MR1[bit12 only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A ...
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... DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent. Figure 2.4.7.2 Write leveling sequence [DQS - DQS# is capturing CK-CK# low at T1 and CK-CK# high at T2] Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... If the ASR mode is not enabled (MR2 bit.A6 = 0b), the SRT bit (MR2 A7) must be manually programmed with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... ASR enabled (for devices supporting ASR and Extended 1 0 Temperature Range). Self-Refresh power consumption is temperature dependent 1 1 Illegal Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Allowed Operating Temperature Range for Self-Refresh Mode o Normal ( Normal and Extended ( ...
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... If the limit is exceeded, the input levels are covered by the DDR3 specification. 5. With these supply voltages, the device operates with DDR3L specifications. 6. After initialized for DDR3 operation, the DDR3L may be used only upon reset. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... AC input logic high VIL.DQ(AC150) AC input logic low Reference Voltage for VREFDQ(DC) DQ, DM inputs Reference Voltage for VREFDQ_t(DC) trained DQ, DM inputs Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3-800/1066/1333/1600 Parameter Vref + 0.100 Vref + 0.175 Vref + 0.150 0.49 * VDD DDR3L-800/1066/1333/1600 Parameter Vref + 0 ...
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... To allow VREFDQ margining, all DRAM Data Input Buffers MUST use external VREF (provided by system) as the input for their VREFDQ pins. All VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Data input buffer Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A ...
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... Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in DRAM timing and their associated de-ratings. Figure 4.2 Illustration of Vref(DC) tolerance and Vrefac-noise limits Voltage Vref(D C) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Vref ac-noise VDD Vref(t) ...
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... These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A ...
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... VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. VDD or VDDQ VSEHmin VDD/2 or VDDQ/2 VSELmax VSS or VSSQ Figure 4.3.3 Single-ended requirement for differential signals. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 min max 75 - ...
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... See “Address / Command Setup, Hold and Derating” for single-ended slew rate definitions for address and command signals. See “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data signals. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Differential input slew rate for falling edge (CK-CK# & DQS- DQS#) Note : The differential signal (i.e., CK-CK# & DQS-DQS#) must be linear between these thresholds. Figure 4.6.1 Input Nominal Slew Rate Definition for DQS, DQS# and CK, CK# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Measured ...
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... Single ended output slew rate for falling edge 5.3.2 Output Slew Rate (single-ended) Parameter Single-ended Output Slew Rate Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). se: Single-ended signals. For Ron = RZQ/7 setting. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Parameter Parameter ...
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... System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. CK,CK# Figure 5.5 Reference Load for AC Timing and Output Slew Rate Integrated Silicon Solution, Inc. – ...
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... The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu = [VDDQ-Vout Iout | ------------------- under the condition that RONPd is turned off (1) RONPd = Vout / | Iout | -------------------------------under the condition that RONPu is turned off (2) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... DDR3L (assuming 1.35V RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration) , RONNom Resistor RON34Pd 34 ohms RON34Pu 40 ohms RON40Pd 40 ohms RON40Pu Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Chip in Drive Mode Output Driver I Pu RONPu RONPd I Pd Vout VOLdc=0 ...
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... RONPU@VOHdc 0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl RON@VOMdc 0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl RONPD@VOLdc 0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 VOMdc=0.5xVDDQ VOHdc=0.8xVDDQ VOMdc= 0.5xVDDQ Min. ...
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... The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines: Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) respectively. RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))] 6. Measurement definition for VM and DVM: Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Resistor Vout VOLdc = 0 ...
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... Rising edge defined by the end point of ODTLcnw, t ADC ODTLcwn4, or ODTLcwn8 Reference Settings for ODT Timing Measurements Measured Parameter RTT_Nom Setting t AON t AONPD t AOFPD Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 max 1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl Max 1.5 0.15 VDDQ DQ,DM DUT DQS, DQS#, ...
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... Figure 5.9.2.1 Definition of t AON CK CK# DQ,DM,DQS, DQS#,TDQS, TDQS# Figure 5.9.2.2 Definition of t AONPD CK CK# DQ,DM,DQS, DQS#,TDQS, TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 RZQ/12 NA RZQ/12 RZQ/2 Begin Point : Rising edge of CK-CK# defined by the end of ODTLon t AON Tsw2 Tsw1 Vsw1 ...
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... DQ,DM,DQS, DQS#,TDQS, TDQS# Figure 5.9.2.4 Definition of t AOFPD CK CK# DQ,DM,DQS, DQS#,TDQS, TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Begin Point : Rising edge of CK-CK# with defined by the end point of ODTLoff t AOF V End Point : Extrapolated point at V RTT_NOM Tsw2 ...
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... Begin Point : Rising edge of CK-CK# defined by the end point of ODTLcnw CK CK# End Point : Extrapolated DQ,DM,DQS, point at V DQS#,TDQS, RTT_NOM TDQS# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 Begin Point : Rising edge of CK-CK# defined by the end point of ODTLcwn4 or ODTLcwn8 t t ADC ADC Tsw21 ...
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... C applies to A0-A13, BA0-BA2, RAS#, CAS# and WE# DI_ADD_CMD 10 (ADD_CMD) - 0.5*(C (CK)+C DI_ADD_CMD (DQ,DM) - 0.5*(C (DQS)+C DIO IO IO 12. Maximum external load capacitance on ZQ pin: 5 pF. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3 DDR3/DDR3 L-800 Min Max Min DDR3 1.5 3 1.5 DDR3L 1.5 2.5 1.5 0.8 1 ...
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... IDD5B Burst Refresh Current IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3-1066 DDR3-1333 DDR3-1600 Max. Max. Max. TBD 65 70 ...
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... IDD5B Burst Refresh Current IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3-1066 DDR3-1333 DDR3-1600 Max. Max. Max. TBD 72 75 ...
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... IDD5B Burst Refresh Current IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3-1066 DDR3-1333 DDR3-1600 Max. Max. Max. TBD 55 60 ...
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... Burst Refresh Current IDD6 Self-Refresh Current Normal Temperature Range (0-85°C) IDD6ET Self-Refresh Current: extended temperature range IDD7 All Bank Interleave Read Current Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3-1066 DDR3-1333 DDR3-1600 Max. Max. Max. TBD TBD TBD ...
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... DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not subject to production test. 8.1.5 Definition for tJIT(cc), tJIT(cc, Ick) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 tCK(avg ...
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... All Bank Refresh to active/refresh cmd time Average periodic refresh interval Notes: 1. The permissible Tcase operating temperature is specified by temperature grade. The maximum Tcase unless A2 grade, for which the maximum is 105 C. 8.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3-1066MT/s ...
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... ACT to internal read or write delay PRE command period ACT to ACT or REF period ACT to PRE command period CL=5 CWL =5 CWL=6 CWL=7 CWL=8 CL=6 CWL =5 CWL=6 CWL=7 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-1333 9-9-9 (-15H) Symbol Min Max tAA 13.125 20 tRCD 13.125 ...
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... ACT to PRE command period CL=5 CWL =5 CWL=6 CWL=7 CWL=8 CL=6 CWL =5 CWL=6 CWL=7 CWL=8 CL=7 CWL =5 CWL=6 CWL=7 CWL=8 CL=8 CWL =5 CWL=6 CWL=7 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) 1.875 <2.5 tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) 1.875 <2.5 tCK(AVG) ...
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... Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 tCK(AVG) Reserved tCK(AVG) Reserved ...
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... Mode Register Set command cycle time Mode Register Set command update delay ACT to internal read or write delay time PRE command period ACT to ACT or REF command period CAS# to CAS# command delay Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-800 Symbol Min. ...
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... DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-800 Symbol Min. Max. ...
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... Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing Write leveling output delay Write leveling output error Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-800 Symbol Min. ...
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... DQS, DQS# differential output high time DQS, DQS# differential output low time DQS, DQS# differential WRITE Preamble DQS, DQS# differential WRITE Postamble DQS, DQS# rising edge output access time from rising CK, CK# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-1333 Symbol Min. ...
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... Normal operation Short calibration time Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-1333 Symbol Min. Max. tLZ(DQS) ...
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... Down with DLL frozen) Asynchronous RTT turn-off delay (Power- Down with DLL frozen) RTT turn-on RTT_Nom and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-1333 Symbol Min. Max. ...
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... DQ low-impedance time from CK, CK# DQ high impedance time from CK, CK# Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-1333 Symbol Min. Max. ...
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... Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-1866 Symbol Min. ...
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... Timing of WRA command to Power Down entry (BC4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry ODT Timings ODT high time without write command or with write command and BC4 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3/DDR3L-1866 Symbol Min. Max. ...
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... RU{tRP/tCK(avg long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6-Tm) is less than 15ns due to input clock jitter. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 70 ...
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... The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150 mV and another account for the earlier reference point [(175 mv - 150 mV V/ns]. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ...
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... Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] > 2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 < 0.5 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ΔtIS, ΔtIH derating in [ps] AC/DC based CK,CK# Differential Slew Rate 2.0 V/ns 1.8 V/ns ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ...
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... VIH(dc)MIN tangent line VREF(dc) VIL(dc)MAX VIL(ac)MAX Normal slew rate tVAC V SS TF Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 CK# CK tIS tIH V DDQ tVAC VIH(ac)MIN VIH(dc)MIN Normal VREF(dc) slew rate ...
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... VIH/L(ac) tDH(base) DC100 VIH/L(dc) Symbol Reference tDS(base) AC160 VIH/L(ac) tDS(base) AC135 VIH/L(ac) tDH(base) DC90 VIH/L(dc) NOTE: (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DDR3-800 DDR3-1066 75 25 125 75 150 100 DDR3L-800 ...
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... NOTE 1. Cell contents shaded in red are defined as ‘not supported’. 9.6.4 Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] Slew Rate [V/ns] > 2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 < 0.5 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 tDS, DH derating in [ps] AC/DC based A A DQS, DQS# Differential Slew Rate 2.0 V/ns 1.8 V/ns AtDH AtDS AtDH AtDS ...
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... VREF(dc) tangent line VIL(dc)MAX VIL(ac)MAX Normal slew rate tVAC V SS TF Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 DQS# DQS V tDS tDH DDQ tVAC VIH(ac)MIN VIH(dc)MIN Normal VREF(dc) ...
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... C Order Part No. 7-7-7 IS46TR16128A -187FBLA1 9-9-9 IS46TR16128A -15HBLA1 IS46TR16128A -125KBLA1 ≤ 105°C) C Order Part No. 7-7-7 IS46TR16128A -187FBLA2 9-9-9 IS46TR16128A -15HBLA2 IS46TR16128A -125KBLA2 Package 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free Package 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free Package 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free ...
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... C Order Part No. 7-7-7 IS46TR16128AL -187FBLA1 9-9-9 IS46TR16128AL -15HBLA1 IS46TR16128AL -125KBLA1 ≤ 105°C) C Order Part No. 7-7-7 IS46TR16128AL -187FBLA2 9-9-9 IS46TR16128AL -15HBLA2 IS46TR16128AL -125KBLA2 Package 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free Package 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free Package 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free 96-ball FBGA,Lead-free ...
Page 79
... Automotive, A2 Range: (–40°C ≤ T Data Rate CL-tRCD-tRP 1066MT/s 1333MT/s 1600MT/s 11-11-11 Note: Contact ISSI for availability of options. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ≤ 95°C) C Order Part No. 7-7-7 IS43TR82560A -187FBL 9-9-9 IS43TR82560A -15HBL IS43TR82560A -125KBL ≤ ...
Page 80
... Automotive, A2 Range: (–40°C ≤ T Data Rate CL-tRCD-tRP 1066MT/s 1333MT/s 1600MT/s 11-11-11 Note: Contact ISSI for availability of options. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 ≤ 95°C) C Order Part No. 7-7-7 IS43TR82560AL -187FBL 9-9-9 IS43TR82560AL -15HBL IS43TR82560AL -125KBL ≤ ...
Page 81
... IS43/46TR16128A, IS43/46TR16128AL, IS43/46TR82560A, IS43/46TR82560AL PACKAGE OUTLINE DRAWING 78-ball BGA (8mm x 10.5mm): 0.8mm x 0.8mm Pitch (x8) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 81 ...
Page 82
... IS43/46TR16128A, IS43/46TR16128AL, IS43/46TR82560A, IS43/46TR82560AL PACKAGE OUTLINE DRAWING 96-ball BGA (9mm x 13mm): 0.8mm x 0.8mm Pitch (x16) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A 11/14/2012 82 ...