IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 17

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IS46TR16128A-15HBLA2

Manufacturer Part Number
IS46TR16128A-15HBLA2
Description
DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
Manufacturer
ISSI

Specifications of IS46TR16128A-15HBLA2

Rohs
yes
Data Bus Width
16 bit
Organization
128 M x 16
Package / Case
FBGA-96
Memory Size
2 Gbit
Maximum Clock Frequency
933 MHz
Access Time
13.125 ns
Supply Voltage - Max
1.575 V
Supply Voltage - Min
1.425 V
Maximum Operating Current
65 mA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1. Prior to
issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is
enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register.
The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled.
When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the
MPR disabled (MR3 bit A2 = 0).
Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of
RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR
enable mode. The RESET function is supported during MPR enable mode.
MPR MR3 Register Definition
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
MR3 A[2]
MPR
0b
1b
don’t care (0b or 1b)
See Table 13
MR3 A[1:0]
MPR-Loc
Memory Core
precharged)
(all banks
Normal operation, no MPR transaction. All subsequent Reads will come from DRAM
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
DQ, DM, DQS, DQS#
Figure 2.3.5.1 MPR Block Diagram
MR3[A2]
array. All subsequent Write will go to DRAM array.
Register pre-defined
Multipurpose
data for read
Function
17

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