IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 7

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.2 RESET and Initialization Procedure
2.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
OR
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined).
2. After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM will
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE goes
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further,
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command,
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RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low” anytime before
RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300mV to VDD(min) must be
no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts.
start internal state initialization; this will be done independently of external clocks.
active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also, a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE is
registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is
finished, including expiration of tDLLK and tZQinit.
the SDRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered
HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is
registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled
in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the
power up initialization sequence is finished, including the expiration of tDLLK and tZQinit.
command to load mode register. (tXPR=max (tXS ; 5 x tCK)
BA0 and BA2, “High” to BA1.)
BA2, “High” to BA0 and BA1.)
provide "Low" to A0, "High" to BA0 and "Low" to BA1 – BA2).
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to
0.95 V max once power ramp is finished, AND
Vref tracks VDDQ/2.
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side.
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