IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 32

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Notes:
1. For input only pins except RESET#. Vref = VrefDQ(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than ± 0.1% VDD.
4. For reference: DDR3 has approx. VDD/2 ±15mV, and DDR3L has approx. V
5. Single-ended swing requirement for DQS-DQS#, is 350mV (peak to peak). Differential swing requirement for DQS-DQS#, is 700mV (peak to peak)
6. VRefDQ training is performed only during system boot. Once the training is completed and an optimal VRefDQ_t(DC) voltage level is identified, the
optimal VRefDQ_t(DC) voltage level will be used during system runtime. During VRefDQ training, VRefDQ is swept from 40% of VDD to 60% of VDD to
find the optimal VRefDQ_t(DC) voltage level; and once the optimal VRefDQ_t(DC) is set, it must stay within ±1% of its set value as well as not be less
than 45% of VDD or exceed 55% of VDD. VIH.DQ(AC)min/VIL.DQ(AC)max = Optimal VRefDQ_t(DC) ±AC Level, where "AC Level" is the actual AC
voltage level per DDR3 speed bins as specified in JESD79-3 specification. After VRefDQ training is completed and the optimal VRefDQ_t(DC) is set, the
Memory Controller provides the DRAM device a valid write window. Through DQS placement optimization and VRefDQ centering, the valid write window
is optimized for both input voltage margin and tDS+tDH window for the DRAM receiver. The DRAM device supports the use of the above techniques to
optimize the write timing and voltage margin, as long as the technique does not create any DIMM failures due to DRAM input voltage and/or timing spec
violations as defined in JESD79-3 specification.
7. To allow VREFDQ margining, all DRAM Data Input Buffers MUST use external VREF (provided by system) as the input for their VREFDQ pins. All
VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Data input buffer
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
VIH.DQ(AC160)
VIH.DQ(AC135)
VREFDQ_t(DC)
VIL.DQ(AC160)
VIL.DQ(AC135)
VIH.DQ(DC90)
VIL.DQ(DC90)
VREFDQ(DC)
Symbol
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
Reference Voltage for DQ,
DM inputs
Reference Voltage for
trained DQ, DM inputs
Parameter
Vref +0.175
Vref +0.150
Vref +0.09
0.49 *VDD
0.45 *VDD
Note2
Note2
Min.
VSS
DDR3L-800/1066
Vref -0.160
Vref -0.135
0.51 *VDD
0.55 *VDD
Vref -0.09
DD
Note2
Note2
/2 ± 13.5mV.
Max.
VDD
Vref +0.135
0.49 *VDD
0.45 *VDD
Vref +0.09
Note2
Min.
VSS
DDR3L-1333/1600
-
-
.
Vref -0.135
0.51 *VDD
0.55 *VDD
Vref -0.09
Note2
Max.
VDD
-
-
Unit
V
V
V
V
V
V
V
V
1,2,5
1,2,5
1,2,5
1,2,5
Note
3,4,
3,4
6,7
32
1
1