S9S12G96F0VLH Freescale Semiconductor, S9S12G96F0VLH Datasheet - Page 251

• Manufacturer Part Number: S9S12G96F0VLH
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0VLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

Port Integration Module (S12GPIMV1)
Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not
provided on these pins.
2.5.4.2
Pin Interrupts and Wakeup
Ports P, J and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity
to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share
the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a port interrupt flag (PIF) and its corresponding port interrupt enable (PIE)
are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop or wait mode.
A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is
detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active
level. Else the sampling logic is restarted.
In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of t
PULSE
< n
/f
are assuredly filtered out while pulses with a duration of t
> n
/f
guarantee
P_MASK
bus
PULSE
P_PASS
bus
a pin interrupt.
In stop mode the clock is generated by an RC-oscillator. The minimum pulse length varies over process
conditions, temperature and voltage
(Figure
2-65). Pulses with a duration of t
< t
are
PULSE
P_MASK
assuredly filtered out while pulses with a duration of t
> t
guarantee a wakeup event.
PULSE
P_PASS
Please refer to the appendix table “Pin Interrupt Characteristics” for pulse length limits.
To maximize current saving the RC oscillator is active only if the following condition is true on any
individual pin:
Sample count <= 4 (at active or passive level) and interrupt enabled (PIE=1) and interrupt flag not set
(PIF=0).
Glitch, filtered out, no interrupt flag set
uncertain
Valid pulse, interrupt flag set
t
(min) t
(max)
PULSE
PULSE
Figure 2-65. Interrupt Glitch Filter (here: active low level selected)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
253