S9S12G96F0VLH Freescale Semiconductor, S9S12G96F0VLH Datasheet - Page 320

• Manufacturer Part Number: S9S12G96F0VLH
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0VLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

S12S Debug Module (S12SDBGV2)
Read: Anytime
Write: Never
8.3.2.7
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
322
CNT[5:0]
Field
TBF
5–0
7
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGSR[7]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer.
Table 8-13
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in
end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT
register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset
occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer
entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace
buffer.
Debug State Control Registers
TBF
0
0
1
1
shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
Table 8-14. State Control Register Access Encoding
CNT[5:0]
000000
000001
000010
000100
000110
111111
000000
000001
111110
COMRV
..
..
..
MC9S12G Family Reference Manual, Rev.1.23
00
Table 8-12. DBGCNT Field Descriptions
Table 8-13. CNT Decoding Table
oldest data has been overwritten by most recent data
ARM bit will be cleared and the tracing session ends.
Visible State Control Register
64 lines valid; if using Begin trigger alignment,
Description
DBGSCR1
64 lines valid,
No data valid
63 lines valid
Description
2 lines valid
4 lines valid
6 lines valid
1 line valid
..
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