S9S12G96F0MLH Freescale Semiconductor, S9S12G96F0MLH Datasheet - Page 295

• Manufacturer Part Number: S9S12G96F0MLH
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0MLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

When BDM is activated, the CPU finishes executing the current instruction and then begins executing the
firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type
of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0x3_FF00 to 0x3_FFFF. BDM registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses
these registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
When BDM is activated while CPU executes code overlapping with BDM firmware space the saved
program counter (PC) will be auto incremented by one from the BDM firmware, no matter what caused
the entry into BDM active mode (BGND instruction, BACKGROUND command or breakpoints). In such
a case the PC must be set to the next valid address via a WRITE_PC command before executing the GO
command.
7.4.3
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU such
as on-chip RAM, Flash, I/O and control registers.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although, they can still be executed in this mode. When executing a
hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not
disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is
momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation
does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,
if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the
BDM found a free cycle.
The BDM hardware commands are listed in
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations
are not normally in the system memory map but share addresses with the application in memory. To
distinguish between physical memory locations that share the same address, BDM memory resources are
1. This method is provided by the S12S_DBG module.
Freescale Semiconductor
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Hardware BACKGROUND command
CPU BGND instruction
Breakpoint force or tag mechanism
BDM Hardware Commands
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
MC9S12G Family Reference Manual, Rev.1.23
1
Table
NOTE
7-5.
Background Debug Module (S12SBDMV1)
297