S9S12G48F1VLC Freescale Semiconductor, S9S12G48F1VLC Datasheet - Page 695

• Manufacturer Part Number: S9S12G48F1VLC
• Description: 16-bit Microcontrollers - MCU 16 BIT 48K FLASH 4KB RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G48F1VLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge
within the frame. Re synchronization within frames will correct a misalignment between transmitter bit
times and receiver bit times.
20.4.6.5.1
Figure 20-28
a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
Let’s take RTr as receiver RT clock and RTt as transmitter RT clock.
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles
to start data sampling of the stop bit.
With the misaligned character shown in
the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data
character with no errors is:
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles
to start data sampling of the stop bit.
With the misaligned character shown in
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
20.4.6.5.2
Figure 20-29
instead of RT16 but is still sampled at RT8, RT9, and RT10.
Freescale Semiconductor
((151 – 144) / 151) x 100 = 4.63%
((167 – 160) / 167) X 100 = 4.19%
shows how much a slow received frame can be misaligned without causing a noise error or
shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
Slow Data Tolerance
Fast Data Tolerance
RT Clock
Receiver
MC9S12G Family Reference Manual, Rev.1.23
MSB
Figure
Figure
Figure 20-28. Slow Data
20-28, the receiver counts 151 RTr cycles at the point when
20-28, the receiver counts 167 RTr cycles at the point when
Samples
Data
Stop
Serial Communication Interface (S12SCIV5)
697