S9S12G48F1VLC Freescale Semiconductor, S9S12G48F1VLC Datasheet - Page 760

no-image

S9S12G48F1VLC

Manufacturer Part Number
S9S12G48F1VLC
Description
16-bit Microcontrollers - MCU 16 BIT 48K FLASH 4KB RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G48F1VLC

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-32
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12G48F1VLC
Manufacturer:
HUAJING
Quantity:
35 000
Part Number:
S9S12G48F1VLC
Manufacturer:
FREESCALE
Quantity:
5 000
Part Number:
S9S12G48F1VLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S12G48F1VLC
Manufacturer:
FREESCALE
Quantity:
5 000
Timer Module (TIM16B8CV3)
23.3.2.8
Read: Anytime
Write: Anytime
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
762
Module Base + 0x0008
Module Base + 0x0009
Reset
Reset
Field
OMx
OLx
7:0
7:0
W
W
R
R
OM7
OM3
Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For
Output Level — These eightpairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
0
0
7
7
an output line to be driven by an OCx the OCPDx must be cleared.
an output line to be driven by an OCx the OCPDx must be cleared.
OMx
OL7
OL3
0
0
6
6
0
0
1
1
Figure 23-14. Timer Control Register 1 (TCTL1)
Figure 23-15. Timer Control Register 2 (TCTL2)
Table 23-8. TCTL1/TCTL2 Field Descriptions
Table 23-9. Compare Result Output Action
MC9S12G Family Reference Manual,
OM6
OM2
OLx
0
1
0
1
0
0
5
5
OL6
OL2
0
0
4
4
action on the timer output signal
Clear OCx output line to zero
Description
Set OCx output line to one
Toggle OCx output line
No output compare
OM5
OM1
Action
0
0
3
3
Rev.1.23
OL5
OL1
0
0
2
2
Freescale Semiconductor
OM4
OM0
0
0
1
1
OL4
OL0
0
0
0
0

Related parts for S9S12G48F1VLC