S9S12GN48F1VLC Freescale Semiconductor, S9S12GN48F1VLC Datasheet - Page 329

• Manufacturer Part Number: S9S12GN48F1VLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN48F1VLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

8.3.2.8.5
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
8.3.2.8.6
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
Freescale Semiconductor
Address: 0x002C
Address: 0x002D
Bits[15:8]
Bits[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
Bit 15
Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
Bit 7
Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected
comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
0
0
7
7
Debug Comparator Data High Register (DBGADH)
Debug Comparator Data Low Register (DBGADL)
Figure 8-19. Debug Comparator Data High Register (DBGADH)
Figure 8-20. Debug Comparator Data Low Register (DBGADL)
Bit 14
Bit 6
0
0
6
6
MC9S12G Family Reference Manual, Rev.1.23
Table 8-28. DBGADH Field Descriptions
Table 8-29. DBGADL Field Descriptions
Bit 13
Bit 5
0
0
5
5
Bit 12
Bit 4
0
0
4
4
Description
Description
Bit 11
Bit 3
0
0
3
3
Bit 10
Bit 2
0
0
2
2
S12S Debug Module (S12SDBGV2)
Bit 9
Bit 1
0
0
1
1
Bit 8
Bit 0
0
0
0
0
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