S9S12GN48F1VLC Freescale Semiconductor, S9S12GN48F1VLC Datasheet - Page 598

• Manufacturer Part Number: S9S12GN48F1VLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN48F1VLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

Freescale’s Scalable Controller Area Network (S12MSCANV3)
1
18.3.2.8
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
600
Module Base + 0x0006
Module Base + 0x0007
Read: Anytime
Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored
TXE[2:0]
Field
2-0
Reset:
Reset:
W
W
R
R
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 18.3.2.9, “MSCAN Transmitter Message Abort Request Register
transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see
Message Abort Acknowledge Register
is cleared (see
When listen-mode is active (see
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
MSCAN Transmitter Interrupt Enable Register (CANTIER)
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
0
0
7
7
Figure 18-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
Figure 18-10. MSCAN Transmitter Flag Register (CANTFLG)
Section 18.3.2.9, “MSCAN Transmitter Message Abort Request Register
= Unimplemented
= Unimplemented
Table 18-13. CANTFLG Register Field Descriptions
6
0
0
6
0
0
MC9S12G Family Reference Manual,
Section 18.3.2.2, “MSCAN Control Register 1
0
0
0
0
5
5
(CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
NOTE
4
0
0
4
0
0
Description
0
0
0
0
3
3
Rev.1.23
Section 18.3.2.10, “MSCAN Transmitter
TXEIE2
(CANTARQ)”). If not masked, a
TXE2
2
1
2
0
(CANCTL1)”) the TXEx flags
Access: User read/write
Access: User read/write
Freescale Semiconductor
TXEIE1
TXE1
(CANTARQ)”).
1
0
1
1
TXEIE0
TXE0
0
1
0
0
1
1