S9S12GN48F1VLC Freescale Semiconductor, S9S12GN48F1VLC Datasheet - Page 333

• Manufacturer Part Number: S9S12GN48F1VLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN48F1VLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

8.4.2.1.2
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is
set the access size (word or byte) is compared with the SZ bit value such that only the specified size of
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in
8.4.2.1.3
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table 8-34
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in
Freescale Semiconductor
1
1
SZE
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
0
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
Word and byte accesses of ADDR[n]
Word accesses of ADDR[n] only
Byte accesses of ADDR[n] only
Read and write accesses of ADDR[n]
Condition For Valid Match
SZ
X
Table
Condition For Valid Match
Read accesses of ADDR[n]
lists access considerations with data bus comparison. On word accesses the data byte of the
Write accesses of ADDR[n]
DBGADHM,
DBGADLM
Comparator B
Comparator A
$0000
8-33.
Table
Table 8-34. Comparator A Matches When Accessing ADDR[n]
8-32.
Byte
Word
Table 8-33. Comparator B Access Size Considerations
Table 8-32. Comparator C Access Considerations
MC9S12G Family Reference Manual, Rev.1.23
DH=DBGADH, DL=DBGADL
Comp B Address RWE
ADDR[n]
ADDR[n]
ADDR[n]
Access
Comp C Address RWE
ADDR[n]
1
ADDR[n]
ADDR[n]
1
0
0
0
SZE
0
1
1
0
1
1
Table
SZ8
No databus comparison
RW
X
0
1
X
0
1
8-32.
S12S Debug Module (S12SDBGV2)
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
MOVB #$BYTE ADDR[n]
MOVB #$BYTE ADDR[n]
STAA #$BYTE ADDR[n]
STAA #$BYTE ADDR[n]
LDAA #$BYTE ADDR[n]
Comment
LDAB ADDR[n]
LDAA ADDR[n]
LDD ADDR[n]
Examples
Examples
335