S9S12G240F0CLFR Freescale Semiconductor, S9S12G240F0CLFR Datasheet - Page 349

• Manufacturer Part Number: S9S12G240F0CLFR
• Description: 16-bit Microcontrollers - MCU 16BIT 240KB FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G240F0CLFR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 240 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

8.5.6
Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C.
Scenario 5 is possible with the S12SDBGV1 SCR encoding
8.5.7
Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is
not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The
change in SCR1 encoding also has the advantage that a State1->State3 transition using M0 is now possible.
This is advantageous because range and data bus comparisons use channel0 only.
8.5.8
Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run
in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the
S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding
OR forks as shown in red this scenario is possible.
Freescale Semiconductor
SCR1=1101
State1
Scenario 5
Scenario 6
Scenario 7
SCR1=0011
SCR1=1001
State1
State1
M1
SCR2=1100
MC9S12G Family Reference Manual, Rev.1.23
State2
M1
M0
M2
M12
M0
SCR2=0110
SCR3=1010
Figure 8-34. Scenario 5
Figure 8-35. Scenario 6
Figure 8-36. Scenario 7
State2
State3
M2
M02
SCR3=1101
M0
M0
State3
M01
Final State
Final State
M12
Final State
S12S Debug Module (S12SDBGV2)
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