S9S12G240F0CLFR Freescale Semiconductor, S9S12G240F0CLFR Datasheet - Page 409

• Manufacturer Part Number: S9S12G240F0CLFR
• Description: 16-bit Microcontrollers - MCU 16BIT 240KB FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G240F0CLFR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 240 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

This mode can be entered from default mode PEI by performing the following steps:
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
10.5
10.5.1
All reset sources are listed in
priorities.
10.5.2
Upon detection of any reset of
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 10-27
Freescale Semiconductor
1. Make sure the PLL configuration is valid.
2. Enable the external oscillator (OSCE bit)
3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).
4. Clear all flags in the CPMUFLG register to be able to detect any status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
6. Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)
•
•
•
PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
The OSCCLK provided to the MSCAN module is off.
Resets
General
Description of Reset Operation
shows which vector will be fetched.
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
External pin RESET
Clock Monitor Reset
Reset Source
COP Reset
Table
Table
MC9S12G Family Reference Manual, Rev.1.23
10-26. Refer to MCU specification for related vector addresses and
10-26, an internal circuit drives the RESET pin low for 512 PLLCLK
Table 10-26. Reset Summary
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
S12 Clock, Reset and Power Management Unit (S12CPMU)
Local Enable
None
None
None
None
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