MK22DX128VMC5

Manufacturer Part NumberMK22DX128VMC5
DescriptionARM Microcontrollers - MCU ARM+128KB +USB
ManufacturerFreescale Semiconductor
MK22DX128VMC5 datasheet
 

Specifications of MK22DX128VMC5

RohsyesCoreARM Cortex M4
Processor SeriesK20Data Bus Width32 bit
Maximum Clock Frequency50 MHzProgram Memory Size128 KB
Data Ram Size32 KBOn-chip AdcYes
Operating Supply Voltage1.71 V to 3.6 VOperating Temperature Range- 40 C to + 85 C
Package / CaseMAPBGA-121Mounting StyleSMD/SMT
A/d Bit Size16 bitInterface TypeI2C, I2S, SPI, UART, USB
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Number Of Programmable I/os16Number Of Timers4
On-chip DacYesProgram Memory TypeFlash
Supply Voltage - Max3.6 VSupply Voltage - Min1.71 V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
Page 47/55

Download datasheet (2Mb)Embed
PrevNext
Table 10. Chip power modes (continued)
Chip mode
Description
VLPR (Very Low
On-chip voltage regulator is in a low power mode that supplies only
Power Run)
enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 4 MHz source for the core, the bus and the
peripheral clocks.
VLPW (Very
Same as VLPR but with the core in sleep mode to further reduce
Low Power
power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
Wait) -via WFI
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
VLPS (Very Low
Places chip in static state with LVD operation off. Lowest power mode
Power Stop)-via
with ADC and pin interrupts functional. Peripheral clocks are stopped,
WFI
but LPTimer, RTC, CMP, DAC can be used. NVIC is disabled (FCLK =
OFF); AWIC is used to wake up from interrupt. On-chip voltage
regulator is in a low power mode that supplies only enough power to
run the chip at a reduced frequency. All SRAM is operating (content
retained and I/O states held).
LLS (Low
State retention power mode. Most peripherals are in state retention
Leakage Stop)
mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can
be used. NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
All SRAM is operating (content retained and I/O states held).
VLLS3 (Very
Most peripherals are disabled (with clocks stopped), but LLWU,
Low Leakage
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
Stop3)
used to wake up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
VLLS2 (Very
Most peripherals are disabled (with clocks stopped), but LLWU,
Low Leakage
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
Stop2)
used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
VLLS1 (Very
Most peripherals are disabled (with clocks stopped), but LLWU,
Low Leakage
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
Stop1)
used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
VLLS0 (Very
Most peripherals are disabled (with clocks stopped), but LLWU and
Low Leakage
RTC can be used. NVIC is disabled; LLWU is used to wake up.
Stop 0)
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
The POR detect circuit can be optionally powered off.
K20 Family Product Brief, Rev. 11, 08/2012
Freescale Semiconductor, Inc.
Table continues on the next page...
Power modes
Core mode
Normal
recovery
method
Run
Interrupt
Sleep
Interrupt
Sleep Deep
Interrupt
Sleep Deep
Wakeup
1
Interrupt
2
Sleep Deep
Wakeup Reset
2
Sleep Deep
Wakeup Reset
2
Sleep Deep
Wakeup Reset
2
Sleep Deep
Wakeup Reset
47