STM32F205REY6TR STMicroelectronics, STM32F205REY6TR Datasheet
STM32F205REY6TR
Specifications of STM32F205REY6TR
Available stocks
Related parts for STM32F205REY6TR
STM32F205REY6TR Summary of contents
Page 1
ARM-based 32-bit MCU, 150DMIPs Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features ■ Core: ARM 32-bit Cortex™-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™) allowing ...
Page 2
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
STM32F20xxx 2.2.29 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Contents 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 6 Package characteristics . . . . . . . . . . . . . . . . . . . ...
Page 5
STM32F20xxx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of tables Table 47. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
STM32F20xxx List of figures Figure 1. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package ...
Page 8
List of figures 2 Figure 38 bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
STM32F20xxx Figure 87. USB OTG FS (full speed) host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
... Introduction 1 Introduction This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the The STM32F205xx and STM32F207xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices throughout the document ...
Page 11
STM32F20xxx 2 Description The STM32F20x family is based on the high-performance ARM core operating at a frequency 120 MHz. The family incorporates high-speed embedded memories (Flash memory Mbyte 128 Kbytes of system ...
Page 12
Table 2. STM32F205xx features and peripheral counts Peripherals Flash memory in Kbytes 128 System 64 (SRAM1+SRAM2) (48+16) SRAM in Kbytes Backup FSMC memory controller Ethernet General-purpose Advanced-control Timers Basic IWDG WWDG RTC Random number generator 2 SPI/( ...
Page 13
Table 2. STM32F205xx features and peripheral counts (continued) Peripherals Operating temperatures Package 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only ...
Page 14
Table 3. STM32F207xx features and peripheral counts (continued) Peripherals 2 SPI/( USART UART Comm. interfaces USB OTG FS USB OTG HS CAN Camera interface GPIOs SDIO 12-bit ADC Number of channels 12-bit DAC Number of channels ...
Page 15
STM32F20xxx 2.1 Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom ...
Page 16
Description Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package Two 0 Ω resistors connected to for the STM32F10xx - for the ...
Page 17
STM32F20xxx 2.2 Device overview Figure 4. STM32F20x block diagram NJTRST, JTDI, JTCK/SWCLK JTAG & SW JTDO/SWD JTDO/TRACESWO ETM TRACECLK TRACED[3:0] ARM Cortex-M3 120 MHz ART accelerator MII or RMII as AF Ethernet MAC MDIO as AF 10/100 USB DP, DM ...
Page 18
Description ® 2.2.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, ...
Page 19
STM32F20xxx 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to ...
Page 20
Description 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer ...
Page 21
STM32F20xxx 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F20x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M3. The NVIC ...
Page 22
Description 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: ● Boot from user Flash ● Boot from system memory ● Boot from embedded SRAM The boot loader is located in system ...
Page 23
STM32F20xxx Regulator ON The regulator ON modes are activated by default on LQFP packages.On WLCSP66 package, they are activated by connecting both REGOFF and IRROFF pins to V only REGOFF must be connected minimum value is 1.8 ...
Page 24
Description Figure 6. Startup in regulator OFF: slow V - power-down reset risen after V PDR=1.8 V 1 This figure is valid both whatever the internal reset mode (ON or OFF). Figure 7. Startup in regulator ...
Page 25
STM32F20xxx has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and ...
Page 26
Description 2.2.19 V operation BAT The V pin allows to power the device V BAT external supercapacitor. V operation is activated when V BAT The V pin supplies the RTC, the backup registers and the backup SRAM. BAT Note: When ...
Page 27
STM32F20xxx Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. ...
Page 28
Description output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. ...
Page 29
STM32F20xxx communicate at speeds 7.5 Mbit/s. The other available interfaces communicate 3.75 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) ...
Page 30
Description 2.2.25 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer MHz in 8-bit mode, and ...
Page 31
STM32F20xxx 2.2.27 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames ...
Page 32
Description 2.2.30 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I achieve error-free I performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I disabling the main PLL (PLL) used for ...
Page 33
STM32F20xxx 2.2.33 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down peripheral alternate function. ...
Page 34
Description 2.2.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used ...
Page 35
STM32F20xxx 3 Pinouts and pin description Figure 8. STM32F20x LQFP64 pinout PC13-RTC_AF1 PC14-OSC32_IN PC15-OSC32_OUT PH1-OSC_OUT Figure 9. STM32F20x WLCSP64+2 ballout A VSS_2 VDD_4 E F VSS_4 Top view ...
Page 36
Pinouts and pin description Figure 10. STM32F20x LQFP100 pinout VBAT PC13-RTC_AF1 PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 PH0-OSC_IN PH1-OSC_OUT NRST VDD_12 VSSA VREF+ VDDA PA0-WKUP 1. RFU means “reserved for future use”. This pin can be tied to V 36/177 PE2 1 ...
Page 37
STM32F20xxx Figure 11. STM32F20x LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-RTC_AF1 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 PF3 13 PF4 14 PF5 SS_5 V ...
Page 38
Pinouts and pin description Figure 12. STM32F20x LQFP176 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PI8-RTC_AF2 7 PC13-RTC_AF1 8 PC14-OSC32_IN 9 PC15-OSC32_OUT 10 PI9 11 PI10 12 PI11 SS_13 V 15 ...
Page 39
STM32F20xxx Figure 13. STM32F20x UFBGA176 ballout PE3 PE2 PE1 PE0 B PE4 PE5 PE6 PB9 C VBAT PI7 PI6 PI5 PC13- PI8- D PI9 PI4 TAMP1 TAMP2 PC14- E PF0 PI10 PI11 OSC32_IN PC15- ...
Page 40
Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins - - - - PC14 OSC32_OUT - ...
Page 41
STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins ...
Page 42
Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins ...
Page 43
STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins ...
Page 44
Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins R13 M10 N10 - - - - 83 M11 - - - ...
Page 45
STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins R14 R15 - - P15 - - P14 - - N15 ...
Page 46
Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins - - - 95 114 H13 115 H15 116 G15 117 G14 ...
Page 47
STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins - - - - 128 E12 - - - - 129 E13 - - - - 130 D13 - - - - 131 E14 - - - - 132 D14 ...
Page 48
Pinouts and pin description Table 6. STM32F20x pin and ball definitions (continued) Pins 116 144 D12 - - 84 117 145 D11 - - 85 118 146 D10 - - 86 119 147 C11 - - - ...
Page 49
STM32F20xxx Table 6. STM32F20x pin and ball definitions (continued) Pins 133 161 A10 134 162 135 163 136 164 137 165 B5 ...
Page 50
... Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website: www.st.com. ...
Page 51
STM32F20xxx Table 7. FSMC pin definition (continued) Pins CF PF4 A4 PF5 A5 PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR PF12 A6 PF13 A7 PF14 A8 PF15 A9 PG0 A10 PG1 PE7 D4 PE8 D5 PE9 D6 ...
Page 52
Pinouts and pin description Table 7. FSMC pin definition (continued) Pins CF PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 NWE PD6 NWAIT PD7 PG9 PG10 NCE4_1 PG11 NCE4_2 PG12 PG13 PG14 PB7 PE0 PE1 52/177 FSMC ...
Page 53
Table 8. Alternate function mapping AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PA0-WKUP TIM2_CH1_ETR TIM 5_CH1 TIM8_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 PA5 TIM2_CH1_ETR TIM8_CH1N PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN PA7 TIM1_CH1N ...
Page 54
Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PB14 TIM1_CH2N TIM8_CH2N PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N PC0 PC1 PC2 PC3 PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 PC9 MCO2 TIM3_CH4 ...
Page 55
Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PD14 TIM4_CH3 PD15 TIM4_CH4 PE0 TIM4_ETR PE1 PE2 TRACECLK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 TIM9_CH1 PE6 TRACED3 TIM9_CH2 PE7 TIM1_ETR PE8 TIM1_CH1N PE9 TIM1_CH1 ...
Page 56
Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PF15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 - OSC_IN PH1 - OSC_OUT PH2 PH3 ...
Page 57
Table 8. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PH14 TIM8_CH2N PH15 TIM8_CH3N PI0 TIM5_CH4 PI1 PI2 TIM8_CH4 PI3 TIM8_ETR PI4 TIM8_BKIN PI5 TIM8_CH1 PI6 TIM8_CH2 PI7 TIM8_CH3 PI8 PI9 PI10 PI11 AF4 AF5 ...
Page 58
Memory mapping 4 Memory mapping The memory map is shown in 58/177 Figure 14. Doc ID 15818 Rev 9 STM32F20xxx ...
Page 59
STM32F20xxx Figure 14. Memory map 0xFFFF FFFF 512-Mbyte block 7 Cortex-M3's internal 0xE000 0000 peripherals 0xDFFF FFFF 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC registers 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank ...
Page 60
Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
Page 61
STM32F20xxx 5.1.6 Power supply scheme Figure 17. Power supply scheme 1.8-3 I/Os 2 × 2.2 μ 1/2/...14/15 15 × 100 × 4.7 μF 1/2/...14/15 REGOFF IRROFF REF 100 nF 100 ...
Page 62
Electrical characteristics 5.1.7 Current consumption measurement Figure 18. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 10: Current permanent damage to the device. These are stress ratings only and functional operation ...
Page 63
STM32F20xxx Table 10. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin Injected ...
Page 64
Electrical characteristics Table 12. General operating conditions (continued) Symbol Parameter V Internal core voltage to be supplied CAP1 externally in REGOFF mode V CAP2 Power dissipation suffix 105 °C for suffix 7 ...
Page 65
STM32F20xxx Table 13. Limitations depending on the operating power supply range Maximum Operating power ADC supply operation range frequency (f 24 MHz with Conversion time up to 2.7 V memory wait 2 Msps 30 MHz ...
Page 66
Electrical characteristics Figure 19. Number of wait states versus The supply voltage can drop to 1.7 V when the device operates in the °C temperature range ...
Page 67
STM32F20xxx 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for T Table 15. Operating conditions at power-up / power-down (regulator ON) Symbol VDD V DD 5.3.4 Operating conditions at power-up / ...
Page 68
Electrical characteristics 5.3.5 Embedded reset and power control block characteristics The parameters given in temperature and V Table 17. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis PVDhyst Power-on/power-down ...
Page 69
STM32F20xxx Table 17. Embedded reset and power control block characteristics (continued) Symbol Brownout level 1 V BOR1 threshold Brownout level 2 V BOR2 threshold Brownout level 3 V BOR3 threshold (2) V BOR hysteresis BORhyst (2)(3) T Reset temporization RSTTEMPO ...
Page 70
Electrical characteristics Typical and maximum current consumption The MCU is placed under the following conditions: ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled except explicitly mentioned. ● ...
Page 71
STM32F20xxx Table 19. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM Symbol Parameter Supply current Run mode 1. Code and data processing running from ...
Page 72
Electrical characteristics Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals Figure 22. Typical current consumption vs temperature, Run mode, code with data ...
Page 73
STM32F20xxx Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 Figure 24. Typical current consumption vs temperature, Run mode, ...
Page 74
Electrical characteristics Table 20. Typical and maximum current consumption in Sleep mode Symbol Parameter External clock all peripherals enabled Supply current Sleep mode External clock peripherals disabled 1. Based on characterization, tested in production ...
Page 75
STM32F20xxx Figure 25. Typical current consumption vs temperature in Sleep mode, peripherals Figure 26. Typical current consumption vs temperature in Sleep mode, peripherals OFF ...
Page 76
Electrical characteristics Table 21. Typical and maximum current consumptions in Stop mode Symbol Parameter Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode with main Flash in ...
Page 77
STM32F20xxx Table 22. Typical and maximum current consumptions in Standby mode Symbol Parameter Backup SRAM ON, low-speed oscillator and RTC ON Supply current Backup SRAM OFF, low Standby DD_STBY speed oscillator and RTC ON mode Backup SRAM ON, ...
Page 78
Electrical characteristics ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled unless otherwise mentioned ● The given value is calculated by measuring the current consumption – with all peripherals clocked off ...
Page 79
STM32F20xxx Table 24. Peripheral current consumption (continued) Peripheral APB1 (1) Typical consumption at 25 °C TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 SPI2 SPI3 CAN1 CAN2 (2) DAC channel 1 (3) ...
Page 80
Electrical characteristics Table 24. Peripheral current consumption (continued) Peripheral APB2 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in ...
Page 81
STM32F20xxx 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 26. High-speed external user clock characteristics ...
Page 82
Electrical characteristics Figure 28. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 29. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...
Page 83
STM32F20xxx Table 28. HSE 4-26 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F I HSE current consumption DD g Oscillator transconductance m (3) t Startup time SU(HSE 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. ...
Page 84
Electrical characteristics Table 29. LSE oscillator characteristics (f Symbol R Feedback resistor F I LSE current consumption DD g Oscillator Transconductance m (2) t startup time SU(LSE) 1. Guaranteed by design, not tested in production the startup ...
Page 85
STM32F20xxx 5.3.9 Internal clock source characteristics The parameters given in ambient temperature and V High-speed internal (HSI) RC oscillator Table 30. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC HSI oscillator HSI oscillator (3) t ...
Page 86
Electrical characteristics Low-speed internal (LSI) RC oscillator Table 31. LSI oscillator characteristics Symbol (2) f Frequency LSI (3) t LSI oscillator startup time su(LSI) (3) I LSI oscillator power consumption DD(LSI –40 to ...
Page 87
STM32F20xxx Table 32. Main PLL characteristics (continued) Symbol Parameter t PLL lock time LOCK Cycle-to-cycle jitter Period Jitter (3) Jitter Main clock output (MCO) for RMII Ethernet Main clock output (MCO) for MII Ethernet Bit Time CAN jitter (4) I ...
Page 88
Electrical characteristics Table 33. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Master I2S clock jitter (3) Jitter WS I2S clock jitter PLLI2S power consumption on (4) I DD(PLLI2S PLLI2S power consumption on (4) I DDA(PLLI2S) V DDA 1. ...
Page 89
STM32F20xxx 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 34. SSCG parameters constraint Symbol f Mod md MODEPER * INCSTEP 1. Guaranteed by design, not tested ...
Page 90
Electrical characteristics Figure 34 and Figure 35 down spread modes, where PLL_OUT T is the modulation period. mode md is the modulation depth. Figure 34. PLL output clock waveforms in center spread mode Frequency (PLL_OUT) Figure 35. ...
Page 91
STM32F20xxx Table 36. Flash memory programming Symbol t Word programming time prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ME V Programming ...
Page 92
Electrical characteristics Table 37. Flash memory programming with V Symbol Minimum current sunk the V Cumulative time during (3) t VPP which V 1. Guaranteed by design, not tested in production. 2. The ...
Page 93
STM32F20xxx Table 39. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce a functional disturbance Fast transient voltage burst limits applied through 100 EFTB pins to induce ...
Page 94
Electrical characteristics Table 40. EMI characteristics Symbol Parameter package, conforming to SAE J1752/3 EEMBC, code running with ART enabled S Peak level EMI = 3 package, conforming to SAE J1752/3 ...
Page 95
STM32F20xxx Table 42. Electrical sensitivities Symbol Parameter LU Static latch-up class 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O pins) ...
Page 96
Electrical characteristics 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 44. I/O static characteristics Symbol Parameter V Input low level voltage IL (2) TT I/O input ...
Page 97
STM32F20xxx All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and ...
Page 98
Electrical characteristics 4. Based on characterization data, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 46, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature ...
Page 99
STM32F20xxx Table 46. I/O AC characteristics OSPEEDRy [1:0] bit Symbol (1) value F Maximum frequency max(IO)out 11 Output high to low level fall t f(IO)out time Output low to high level rise t r(IO)out time Pulse width of external signals ...
Page 100
Electrical characteristics 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology connected to a permanent pull-up resistor, R (see PU Unless otherwise specified, the parameters given in performed under the ambient temperature and V in ...
Page 101
STM32F20xxx 5.3.18 TIM timer characteristics The parameters given in Refer to Section 5.3.16: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 48. Characteristics of TIMx connected to the APB1 domain Symbol t Timer resolution ...
Page 102
Electrical characteristics Table 49. Characteristics of TIMx connected to the APB2 domain Symbol t Timer resolution time res(TIM) Timer external clock f EXT frequency on CH1 to CH4 Res Timer resolution TIM 16-bit counter clock period t when internal clock ...
Page 103
STM32F20xxx 2 Table 50 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t r(SCL) ...
Page 104
Electrical characteristics 2 Figure 38 bus AC waveforms and measurement circuit I²C bus S TART SDA t f(SDA) t h(STA) SCL t w(SCLH) 1. Measurement points are done at CMOS levels: 0.3V Table 51. SCL frequency (f 1. ...
Page 105
STM32F20xxx SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.16: I/O port characteristics function characteristics (NSS, ...
Page 106
Electrical characteristics Figure 39. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...
Page 107
STM32F20xxx Figure 41. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT t c(SCK) t w(SCKH) t w(SCKL) MS BIN ...
Page 108
Electrical characteristics 2 Table 53 characteristics Symbol Parameter clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( valid time v(WS) ( ...
Page 109
STM32F20xxx 2 Figure 42 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. ...
Page 110
Electrical characteristics USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Spee the USB OTG HS and USB OTG FS controllers. Table 54. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested ...
Page 111
STM32F20xxx Figure 44. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines V CRS Table 56. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time f ...
Page 112
Electrical characteristics Figure 45. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) Table 59. ULPI timing Symbol Control in (ULPI_DIR) setup time t SC Control in (ULPI_NXT) setup time t Control ...
Page 113
STM32F20xxx Figure 46. Ethernet SMI timing diagram ETH_MDC ETH_MDIO(O) ETH_MDIO(I) Table 61. Dynamics characteristics: Ethernet MAC signals for SMI Symbol t MDC cycle time (2.38 MHz) MDC t MDIO write data valid time d(MDIO) t Read data setup time su(MDIO) ...
Page 114
Electrical characteristics Table 63 gives the list of Ethernet MAC signals for MII and corresponding timing diagram. Figure 48. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] Table 63. Dynamics characteristics: Ethernet MAC signals for MII Symbol ...
Page 115
STM32F20xxx 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in Table 64. ADC characteristics Symbol Parameter V Power supply DDA V Positive reference voltage REF+ f ADC clock frequency ...
Page 116
Electrical characteristics Table 64. ADC characteristics (continued) Symbol Parameter Sampling rate ( MHz) ADC ADC V DC current (3) REF I VREF+ consumption in conversion mode ADC VDDA DC current (3) I VDDA consumption in ...
Page 117
STM32F20xxx a Table 65. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. Better performance could be achieved in restricted V 2. Based on characterization, not tested ...
Page 118
Electrical characteristics Figure 50. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance ...
Page 119
STM32F20xxx General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference decoupling ...
Page 120
Electrical characteristics 5.3.21 DAC electrical characteristics Table 66. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (2) R Resistive load with buffer ON LOAD Impedance output with buffer ( ...
Page 121
STM32F20xxx Table 66. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (4) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error (difference ...
Page 122
Electrical characteristics Figure 53. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. ...
Page 123
STM32F20xxx 5.3.24 Embedded reference voltage The parameters given in temperature and V Table 69. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage V ...
Page 124
Electrical characteristics Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE ...
Page 125
STM32F20xxx Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NE low ...
Page 126
Electrical characteristics Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 72. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...
Page 127
STM32F20xxx Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 73. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low tim ...
Page 128
Electrical characteristics Synchronous waveforms and timings Figure 58 through Table 77 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...
Page 129
STM32F20xxx Table 74. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low d(CLKL-NADVL) t FSMC_CLK low ...
Page 130
Electrical characteristics Figure 59. Synchronous multiplexed PSRAM write timings FSMC_CLK FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:16] FSMC_NWE t d(CLKL-ADV) FSMC_AD[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL Table 75. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t ...
Page 131
STM32F20xxx Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) Table 76. Synchronous non-multiplexed NOR/PSRAM read ...
Page 132
Electrical characteristics Figure 61. Synchronous non-multiplexed PSRAM write timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL Table 77. Synchronous non-multiplexed PSRAM write timings Symbol t FSMC_CLK period ...
Page 133
STM32F20xxx PC Card/CompactFlash controller waveforms and timings Figure 62 through Table 79 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = ...
Page 134
Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] 134/177 High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID ...
Page 135
STM32F20xxx Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). t v(NCE4_1-A) High t d(NREG-NCE4_1) ...
Page 136
Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 66. PC Card/CompactFlash controller ...
Page 137
STM32F20xxx Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD t d(NCE4_1-NIOWR) FSMC_NIOWR FSMC_D[15:0] Table 78. Switching characteristics for PC Card/CF read and write cycles in attribute/common space Symbol t FSMC_Ncex ...
Page 138
Electrical characteristics Table 79. Switching characteristics for PC Card/CF read and write cycles in I/O space Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low to ...
Page 139
STM32F20xxx Figure 68. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 69. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15: d(ALE-NOE) h(NOE-ALE) t ...
Page 140
Electrical characteristics Figure 70. NAND controller waveforms for common memory read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Figure 71. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Table 80. ...
Page 141
STM32F20xxx Table 81. Switching characteristics for NAND Flash write cycles Symbol t FSMC_NWE low width w(NWE) t FSMC_NWE low to FSMC_D[15-0] valid v(NWE-D) t FSMC_NWE high to FSMC_D[15-0] invalid h(NWE-D) t FSMC_D[15-0] valid before FSMC_NWE high d(D-NWE) t FSMC_ALE valid ...
Page 142
Electrical characteristics Figure 73. SD default mode Table 83 MMC characteristics Symbol Clock frequency in data transfer f PP mode - SDIO_CK/f t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time ...
Page 143
STM32F20xxx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are ...
Page 144
Package characteristics Figure 74. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. Table 85. LQFP64 – pin low-profile quad flat package mechanical ...
Page 145
STM32F20xxx Figure 75. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters 0.5 12.7 10.3 10 7.8 12.7 Doc ID 15818 Rev 9 Package characteristics 0 1.2 ai14909 ...
Page 146
Package characteristics Figure 76. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline A1 ball location D Wafer back side Detail A rotated by 90 °C eee 1. Drawing is not to scale. Table 86. WLCSP64+2 - 0.400 ...
Page 147
STM32F20xxx Figure 77. LQFP100 100-pin low-profile quad flat package outline b Pin 1 identification 1. Drawing is not to scale. Table 87. LQPF100 – 100-pin low-profile quad flat package mechanical data Symbol ...
Page 148
Package characteristics Figure 78. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 148/177 75 76 0.5 16.7 14.3 100 1 12.3 16.7 Doc ID 15818 Rev 9 STM32F20xxx 51 50 0.3 26 1.2 25 ai14906 ...
Page 149
STM32F20xxx Figure 79. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane 1. Drawing is not to scale. Table 88. LQFP144 mm, 144-pin low-profile quad flat package mechanical data Symbol Min A A1 ...
Page 150
Package characteristics Figure 80. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 150/177 108 109 0.35 0.5 19.9 144 1 19.9 22.6 Doc ID 15818 Rev 9 STM32F20xxx 1. 17.85 22 ...
Page 151
STM32F20xxx Figure 81. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline C Seating plane Pin 1 identification 1. Drawing is not to scale. Table 89. LQFP176 - Low profile quad flat package 24 ...
Page 152
Package characteristics Figure 82. LQFP176 recommended footprint 1. Dimensions are expressed in millimeters. 152/177 176 21.8 26.7 Doc ID 15818 Rev 9 STM32F20xxx 1.2 133 0.5 132 0 1.2 1T_FP_V1 ...
Page 153
STM32F20xxx Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Seating plane BOTTOM VIEW 1. Drawing is not to scale. Table 90. ...
Page 154
Package characteristics 6.2 Thermal characteristics The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ is the package junction-to-ambient thermal resistance, in °C/W, ● JA ● P max ...
Page 155
STM32F20xxx 7 Part numbering Table 92. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 205 = STM32F20x, connectivity, 207= STM32F20x, connectivity, camera interface, Ethernet Pin count ( ...
Page 156
Application block diagrams Appendix A Application block diagrams A.1 Main applications versus package Table 93 gives examples of configurations for each package. Table 93. Main applications versus package for STM32F2xxx microcontrollers (1) 64 pins Config Config 1 2 OTG - ...
Page 157
STM32F20xxx A.2 Application example with regulator OFF Figure 84. Regulator OFF/internal reset ON Power-down reset risen after VCAP_1/VCAP_2 stabilization Application reset signal (optional (1.8 to 3.6 V) PA0 VDD REGOFF 1.2 V VCAP_1 VCAP_2 1. This mode is ...
Page 158
Application block diagrams A.3 USB OTG full speed (FS) interface solutions Figure 86. USB OTG FS (full speed) device-only connection OSC_IN OSC_OUT 1. The same application can be developed using the OTG mode to achieve enhanced performance ...
Page 159
STM32F20xxx Figure 88. OTG FS (full speed) connection dual-role with internal PHY STM32F20xxx OSC_IN OSC_OUT 1. External voltage regulator only needed when building The current limiter is required only if the application has to support a V ...
Page 160
Application block diagrams A.4 USB OTG high speed (HS) interface solutions Figure 89. OTG HS (high speed) device connection, host and dual-role in high-speed mode with external PHY STM32F20xxx USB HS OTG Ctrl ULPI PLL possible to ...
Page 161
STM32F20xxx A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 90 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% error maximum, ...
Page 162
Application block diagrams Figure 92. Audio player solution using PLL, PLLI2S, USB and 1 crystal XTAL 25 MHz or 14.7456 MHz MCO1PRE MCO1/ MCO2PRE MCO2 MCLK in Figure 93. Audio PLL (PLLI2S) providing accurate I2S clock 1 MHz CLKIN /M ...
Page 163
STM32F20xxx Figure 94. Master clock (MCK) used to drive the external audio DAC I2S_CK /I2SD 2,3,4,..,129 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 95. Master clock (MCK) not ...
Page 164
Application block diagrams A.6 Ethernet interface solutions Figure 96. MII mode using a 25 MHz crystal MCU HCLK (1) Timer input trigger TIM2 XTAL OSC 25 MHz 1. f must be greater than 25 MHz. HCLK 2. Pulse per second ...
Page 165
STM32F20xxx Figure 98. RMII with a 25 MHz crystal and PHY with PLL MCU HCLK (1) TIM2 2 MHz XTAL OSC 25 MHz 1. f must be greater than 25 MHz. HCLK 2. The 25 MHz (PHY_CLK) must ...
Page 166
Revision history 8 Revision history Table 94. Document revision history Date Revision 05-Jun-2009 09-Oct-2009 01-Feb-2010 13-Jul-2010 166/177 1 Initial release. Document status promoted from Target specification to Preliminary data. In Table 6: STM32F20x pin and ball – Note 4 updated ...
Page 167
STM32F20xxx Table 94. Document revision history (continued) Date Revision 13-Jul-2010 (continued) Added USB OTG_FS features in on-the-go full-speed (OTG_FS). Updated V and V CAP_1 CAP_2 Power supply scheme. Removed DAC, modified ADC limitations, and updated I/O compensation for 1.8 to ...
Page 168
Revision history Table 94. Document revision history (continued) Date Revision 25-Nov-2010 168/177 Update I/Os in Section : Features. Added WLCSP66(64+2) package. Added note 1 related to LQFP176 on cover page. ART accelerator. Added trademark for Adaptive real-time memory accelerator (ART ...
Page 169
STM32F20xxx Table 94. Document revision history (continued) Date Revision 22-Apr-2011 Changed datasheet status to “Full Datasheet”. Introduced concept of SRAM1 and SRAM2. LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices. Availability of WLCSP64+2 ...
Page 170
Revision history Table 94. Document revision history (continued) Date Revision 22-Apr-2011 (continued) 170/177 Updated Typical and maximum current consumption well as Table 18: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ...
Page 171
STM32F20xxx Table 94. Document revision history (continued) Date Revision 22-Apr-2011 (continued) Changed w(SCKH) w(SCLH Table 50: I2C characteristics f(SCK) f(SCL) bus AC waveforms and measurement Added Table 55: USB OTG FS DC electrical ...
Page 172
Revision history Table 94. Document revision history (continued) Date Revision 14-Jun-2011 20-Dec-2011 172/177 Added SDIO in Table 2: STM32F205xx features and peripheral Updated V for 5V tolerant pins in IN Updated jitter parameters description in characteristics. Remove jitter values for ...
Page 173
STM32F20xxx Table 94. Document revision history (continued) Date Revision 20-Dec-2011 (continued) 24-Apr-2012 Added maximum power consumption at T and maximum current consumptions in Stop Updated md minimum value in Added examples in Section 5.3.11: PLL spread spectrum clock generation (SSCG) ...
Page 174
Revision history Table 94. Document revision history (continued) Date Revision 24-Apr-2012 (continued) 174/177 Removed support of I2C for OTG PHY in serial bus on-the-go high-speed Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in STM32F20x pin and ball definitions mapping. Renamed PH10 alternate function ...
Page 175
STM32F20xxx Table 94. Document revision history (continued) Date Revision 29-Oct-2012 Changed minimum supply voltage from 1.65 to 1.8 V. Updated number of AHB buses in Section 2.2.12: Clocks and Removed Figure 4. Compatible board design between STM32F10xx and STM32F2xx for ...
Page 176
Revision history Table 94. Document revision history (continued) Date Revision 29-Oct-2012 (continued) 176/177 Replaced d(CLKL-NOEL) multiplexed NOR/PSRAM read multiplexed NOR/PSRAM read multiplexed NOR/PSRAM read timings non-multiplexed NOR/PSRAM read 10 Added Figure 82: LQFP176 recommended Added Note 2 ...
Page 177
... STM32F20xxx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...