STM32F205REY6TR STMicroelectronics, STM32F205REY6TR Datasheet - Page 175

• Manufacturer Part Number: STM32F205REY6TR
• Description: ARM Microcontrollers - MCU 32-Bit ARM Cortex 512kb Connectivity
• Manufacturer: STMicroelectronics

Specifications of STM32F205REY6TR

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM Cortex M3
• Data Bus Width: 32 bit

STM32F20xxx
Table 94.
29-Oct-2012
Date
Document revision history (continued)
Revision
10
Changed minimum supply voltage from 1.65 to 1.8 V.
Updated number of AHB buses in
Section 2.2.12: Clocks and
Removed Figure 4. Compatible board design between STM32F10xx
and STM32F2xx for LQFP176 package.
Updated
Changed System memory to System memory + OTP in
Memory
Added
Updated V
supply scheme
Changed simplex mode into half-duplex mode in
integrated sound
Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and
DAC_OUT2, respectively.Changed TIM2_CH1/TIM2_ETR into
TIM2_CH1_ETR for PA0 and PA5 in
mapping.
Updated note applying to I
disabled) in
Run mode, code with data processing running from Flash memory
(ART accelerator
and maximum current consumption in Sleep
Removed f
clock
Updated master I2S clock jitter conditions and vlaues in
PLLI2S (audio PLL)
Updated equations in
generation (SSCG)
Swapped TTL and CMOS port conditions for V
Output voltage
Updated V
Updated
characteristics. Removed note 1 related to measurement points below
Figure 40: SPI timing diagram - slave mode and CPHA =
SPI timing diagram - master
diagram (Philips
Updated t
Updated
characteristics: Ethernet MAC signals for SMI
characteristics: Ethernet MAC signals for
Update f
Updated I
Updated note below
decoupling (VREF+ not connected to VDDA)
supply and reference decoupling (VREF+ connected to
Doc ID 15818 Rev 9
characteristics.
Note 1
TRIG
map.
Note 2
Table 52: SPI characteristics
Figure 46: Ethernet SMI timing
HC
DDA
DDA
IL(NRST)
HSE_ext
Table 18: Typical and maximum current consumption in
in
in
description in
below
and V
characteristics.
Table 59: ULPI
and updated
Table 64: ADC
below
protocol)(1).
(I2S).
disabled). Updated
typical value in
and V
characteristics.
characteristics.
Figure 51: Power supply and reference
Table 14: VCAP1/VCAP2 operating
REF+
Section 5.3.11: PLL spread spectrum clock
Figure 4: STM32F20x block
IH(NRST)
decouping capacitor in
DD
startup.
Table 66: DAC
mode, and
Note
(external clock and all peripheral
Changes
timing.
characteristics.
in
Table 26: High-speed external user
Section 2: Description
3.
Table 47: NRST pin
Table 8: Alternate function
Note 3
and
Figure 42: I2S slave timing
diagram,
MII.
Table 53: I2S
characteristics.
below
mode.
and
and
OL
Section 2.2.24: Inter-
and V
Figure 17: Power
Figure 52: Power
Table 61: Dynamics
Table 63: Dynamics
Table 20: Typical
diagram.
Revision history
OH
characteristics.
VDDA).
Figure 14:
Table 33:
and
conditions.
1,
in
Figure 41:
Table 45:
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