74AUP1T57GW,125 NXP Semiconductors, 74AUP1T57GW,125 Datasheet - Page 20

• Manufacturer Part Number: 74AUP1T57GW,125
• Description: IC LP CONFIG GATE V-XLATR UMT6
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1T57GW,125

• Package / Case: SC-70-6, SC-88, SOT-363
• Logic Function: Translator
• Number Of Bits: 2
• Input Type: Voltage
• Output Type: Voltage
• Number Of Channels: 2
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 3.8ns
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Supply Voltage: 2.3 V ~ 3.6 V
• Logic Type: Voltage Level Translator
• Logic Family: AUP
• Input Bias Current (max): 50 mA
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 8.2 ns @ 2.3 V to 2.7 V or 7 ns @ 3 V to 3.6 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Maximum Power Dissipation: 250 mW
• Mounting Style: SMD/SMT
• Number Of Circuits: Configurable
• Data Rate: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74AUP1T57GW-G; 74AUP1T57GW-G; 935280464125

NXP Semiconductors
18. Contents
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6.1
6.2
7
7.1
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15
16
16.1
16.2
16.3
16.4
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18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low-power configurable gate with voltage-level translator
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
For more information, please visit: http://www.nxp.com
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74AUP1T57
Document identifier: 74AUP1T57
Date of release: 21 July 2010
All rights reserved.