iCE40HX8K-CT256 Lattice, iCE40HX8K-CT256 Datasheet
iCE40HX8K-CT256
Specifications of iCE40HX8K-CT256
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iCE40HX8K-CT256 Summary of contents
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... CB132 132-ball BGA CB284 284-ball BGA CT256 256-ball BGA VQ100 100-pin quad flat pack Note 1: At 1.2V VCC © 2007-2012 by Lattice Semiconductor Corporation. All rights reserved. www.latticesemi.com Figure 1: iCE40 HX-Series Family Architectural Features 200 µ kHz (Typical) I/O Bank 0 Programmable Interconnect NVCM ...
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... Ordering Codes (packaged, non-die components Very Thin Quad flat pack (0.5 mm pitch Thin Quad flat pack (0.5 mm pitch) QN iCE40HX8K-CM225 225-ball Chip-Scale BGA Package (7x7 mm footprint, 0.4 mm pitch) ™ Family Package Leads Package Style = chip-scale ball grid (0.4 mm pitch) = chip-scale ball grid (0.5 mm pitch) = chip-scale ball grid (0 ...
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... VPP_2V5 must be connected to a valid voltage, when the iCE40HX device is active. 2. VPP_FAST, used only for fast production programming, must be left floating or unconnected in application. 3. VCCPLL must be tied to VCC when PLL is not used. Lattice Semiconductor Corporation www.latticesemi.com/ Table 2 may cause permanent damage to the device. These are stress ratings only; Table 2: ...
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... NOTE: All characteristics are characterized and may or may not be tested on each pin on each device. Single-ended I/O Characteristics Nominal I/O Bank Supply I/O Standard Voltage LVCMOS33 3.3V LVCMOS25 2.5V LVCMOS18 1.8V LVCMOS15 1.5V Lattice Semiconductor Corporation www.latticesemi.com/ ™ Table 4: PIO Pin Electrical Characteristics Conditions Minimum V = VCCIO max V = VCCIO ...
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... Differential output voltage: Table 7: Recommended Operating Conditions for Differential Outputs VCCIO_x (V) I/O Min Nom Max Standard LVDS 2.38 2.50 2.63 SubLVDS 1.71 1.80 1.89 Lattice Semiconductor Corporation www.latticesemi.com/ Figure 3: Differential Input Specifications Differential input voltage ICM GND Recommended Operating Conditions for Differential Inputs V (mV) ID Min Nom Max ...
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... The following examples provide some guidelines of device performance. The actual performance depends on the specific application and how it is physically implemented in the iCE65P FPGA using the Lattice iCEcube2 software. The following guidelines assume typical conditions (VCC = 1 1 specified, temperature = 25 ˚C). Apply derating factors using the iCEcube2 timing analyzer to adjust to other operating regimes ...
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... PIO Asynchronous delay from adjacent interconnect to PIO output PADO connect pad including interconnect delay. output Lattice Semiconductor Corporation www.latticesemi.com/ The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The Programmable I/O (PIO) Pad-to-Pad Timing Circuit PAD PIO Programmable I/O (PIO) Sequential Timing Circuit ...
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... Write clock High time RMWCKH RCLK RCLK t Write clock Low time RMWCKL t Write clock cycle time RMWCYC F Sustained write clock frequency WMAX Lattice Semiconductor Corporation www.latticesemi.com/ Figure 9: RAM4K Timing Circuit PIO WDATA RAM4K RAM Block (256x16) WCLK Table 10: Typical RAM4K Block Timing Description ™ ...
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... Minimum reset pulse width RST Notes: 1. Output jitter performance is affected by input jitter. A clean reference clock < 100ps jitter must be used to ensure best jitter performance. 2. The output jitter specification refers to the intrinsic jitter of the PLL. Lattice Semiconductor Corporation www.latticesemi.com/ Figure 10: Phase-Locked Loop (PLL) PLL LATCHINPUTVALUE DYNAMICDELAY[3:0] ...
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... Table 12 and the maximum configuration bitstream size from Device Default iCE40HX640 iCE40HX1K iCE40HX4K 230 iCE40HX8K 230 Table 14: General Configuration Timing Description Minimum CRESET_B Low pulse width required to restart configuration, from falling edge to rising edge Number of configuration clock cycles after CDONE goes High before the PIO pins are activated ...
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... Table 17: I/O Bank Static Current ( MHz) Description Static current consumption per I/O bank MHz. No PIO pull-up resistors enabled. All inputs grounded. All outputs driving Low. ™ Family iCE40HX4K iCE40HX8K Typical Typical 667 1100 741 1222 12 13 Typical Maximum « 1 « 1 « ...
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... Initial Release © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...