iCE40HX8K-CT256 Lattice, iCE40HX8K-CT256 Datasheet - Page 10

• Manufacturer Part Number: iCE40HX8K-CT256
• Description: FPGA - Field Programmable Gate Array iCE40HX 7680 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40HX8K-CT256

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 206
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 119

iCE40 HX-Series Ultra-Low Power mobileFPGA
Lattice Semiconductor Corporation
www.latticesemi.com/
Internal Configuration Oscillator Frequency
Configuration Timing
Table 12
Table 13
slowest frequency for a given oscillator mode from
Table 1,
mode based on the performance of the configuration data source.
Table 14
Table 15
f
f
f
Symbol
t
t
t
t
t
t
t
t
t
F
* = Applies after sending the synchronization pattern.
Symbol
OSCD
OSCL
OSCH
Symbol
Symbol
CONFIGL
CRESET_B
DONE_IO
CR_SCK
SUSPISI
HDSPISI
SPISCKH
SPISCKL
SPISCKCYC
SPI_SCK
which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator
provides various timing specifications for the SPI peripheral mode interface.
shows the operating frequency for the iCE40’s internal configuration oscillator.
provides timing for the CRESET_B and CDONE pins.
shows the maximum time to configure an iCE40HX device, by oscillator mode. The calculations use the
Time from when minimum
Power-on Reset (POR)
threshold is reached until
user application starts.
Default
Low
Frequency
High
Frequency
Off
Table 13:
CREST_B
CRESET_B
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
CDONE
From
Oscillator
SPI_SI
From
High
Mode
Description
PIO pins
CREST_B
Typical SPI Master or NVCM Configuration Timing by Oscillator Mode
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
active
SPI_SI
To
To
Table 12:
Frequency (MHz)
Min.
21
35
7
0
Minimum CRESET_B Low pulse width required to restart
configuration, from falling edge to rising edge
Number of configuration clock cycles after CDONE goes
High before the PIO pins are activated.
SPI Peripheral Mode (Clock = SPI_SCK, cycles measured
rising-edge to rising-edge)
Minimum time from a rising edge on CRESET_B until
the first SPI write operation, first SPI_SCK. During this
time, the iCE40HX FPGA is clearing its internal
configuration memory
Setup time on SPI_SI before the rising SPI_SCK clock
edge
Hold time on SPI_SI after the rising SPI_SCK clock edge
SPI_SCK clock High time
SPI_SCK clock Low time
SPI_SCK clock period*
Sustained SPI_SCK clock frequency*
Table 14:
Table 15:
Internal Oscillator Frequency at VCC = 1.2V
Max.
10
30
50
0
iCE40HX640
iCE40HX1K
iCE40HX4K
iCE40HX8K
General Configuration Timing
Device
SPI Peripheral Mode Timing
Default oscillator frequency. Slow enough to safely operate
with any SPI serial PROM.
Supported by most SPI serial Flash PROMs
Supported by some high-speed SPI serial Flash PROMs
Oscillator turned off by default after configuration to save
power.
Table 12
Description
Description
and the maximum configuration bitstream size from
Default
230
230
53
53
™
Family
Description
Low Freq.
110
110
25
25
SPI_SCK frequency
Min.
Min.
200
300
12
12
20
20
40
—
All Grades
All Grades
1
Depends on
High Freq.
(1.31, 30-MAR-2012)
11
11
50
50
1,000
Max.
Max.
49
25
—
—
—
—
—
—
Units
cycles
Units
Units
Clock
MHz
ms
ms
ms
ms
ns
µs
ns
ns
ns
ns
ns
10