iCE40HX8K-CT256 Lattice, iCE40HX8K-CT256 Datasheet - Page 7

• Manufacturer Part Number: iCE40HX8K-CT256
• Description: FPGA - Field Programmable Gate Array iCE40HX 7680 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40HX8K-CT256

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 206
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 119

iCE40 HX-Series Ultra-Low Power mobileFPGA
Lattice Semiconductor Corporation
www.latticesemi.com/
Synchronous Output Paths
t
t
Synchronous Input Paths
t
t
Pad to Pad
t
t
Programmable Input/Output (PIO) Block
OCKO
GBCKIO
SUPDIN
HDPDIN
PADIN
PADO
Table 9
shown in
iCEcube2 development software reports timing adjustments for other I/O standards.
connect
OUTFF
provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
clock
input
GBIN
input
input
GBIN
input
input
Inter-
PIO
PIO
Figure 7
connect
output
output
Table 9:
OUTFF
GBIN
clock
input
input
input
Inter-
PIO
PIO
PIO
and
Figure 8.
Figure 7:
Figure 8:
GBIN
Delay from clock input on OUTFF output flip-flop to PIO output
pad.
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
clock network to clock input on the PIO OUTFF output flip-flop.
Setup time on PIO input pin to INFF input flip-flop before active
clock edge on GBIN input, including interconnect delay.
Hold time on PIO input to INFF input flip-flop after active clock
edge on the GBIN input, including interconnect delay.
Asynchronous delay from PIO input pad to adjacent
interconnect.
Asynchronous delay from adjacent interconnect to PIO output
pad including interconnect delay.
Typical Programmable Input/Output (PIO) Timing (LVCMOS25)
PAD
PAD
Programmable I/O (PIO) Pad-to-Pad Timing Circuit
Programmable I/O (PIO) Sequential Timing Circuit
GBUF
The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The
PIO
PIO
D
Description
INFF
Q
D
OUTFF
™
Family
Q
Nominal VCC
PIO
PIO
PAD
PAD
1.2 V
(1.31, 30-MAR-2012)
Typ.
3.1
1.4
1.6
1.8
3.4
0
units
ns
ns
ns
ns
ns
ns
7