LCMXO2-1200ZE-1TG100C Lattice, LCMXO2-1200ZE-1TG100C Datasheet - Page 10

• Manufacturer Part Number: LCMXO2-1200ZE-1TG100C
• Description: FPGA - Field Programmable Gate Array 1280 LUTs 80 I/O 1.2V -1 SPD
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1TG100C

• Rohs: yes
• Number Of I/os: 80
• Maximum Operating Frequency: 104 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: + 85 C
• Operating Supply Current: 58 uA
• Factory Pack Quantity: 90

The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks
for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals,
MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such
as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the
global clock network for internally-generated global clocks and control signals.
The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteris-
tics table.
The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The
available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2-
640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes The available clock sources
include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs.
Figure 2-5. Primary Clocks for MachXO2 Devices
Up to 8
Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices.
Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL
and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes.
8
11
8
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
2-6
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Enable
Enable
Enable
Enable
Enable
Enable
Clock
Clock
Clock
Clock
Clock
Clock
Switch
Switch
Clock
Clock
Dynamic
Dynamic
Enable
Enable
Clock
Clock
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
Primary Clock 4
Primary Clock 5
MachXO2 Family Data Sheet
Primary Clock 6
Architecture