LCMXO2-1200ZE-1TG100C Lattice, LCMXO2-1200ZE-1TG100C Datasheet - Page 61

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LCMXO2-1200ZE-1TG100C

Manufacturer Part Number
LCMXO2-1200ZE-1TG100C
Description
FPGA - Field Programmable Gate Array 1280 LUTs 80 I/O 1.2V -1 SPD
Manufacturer
Lattice
Datasheet

Specifications of LCMXO2-1200ZE-1TG100C

Rohs
yes
Number Of I/os
80
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Minimum Operating Temperature
+ 85 C
Operating Supply Current
58 uA
Factory Pack Quantity
90

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO2-1200ZE-1TG100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2-1200ZE-1TG100CR1
Manufacturer:
Lattice
Quantity:
87
Part Number:
LCMXO2-1200ZE-1TG100CR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
LPDDR
t
t
t
t
f
f
f
DDR
t
t
t
t
f
f
f
DDR2
t
t
t
t
f
f
f
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other
2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.
5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).
6. For Generic DDRX1 mode t
7. The t
8. This number for general purpose usage. Duty cycle tolerance is +/-10%.
9. Duty cycle is +/- 5% for system usage.
10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.
DVADQ
DVEDQ
DQVBS
DQVAS
DATA
SCLK
LPDDR
DVADQ
DVEDQ
DQVBS
DQVAS
DATA
SCLK
MEM_DDR
DVADQ
DVEDQ
DQVBS
DQVAS
DATA
SCLK
MEM_DDR2
Parameter
operating conditions, including industrial, can be extracted from the Diamond software.
9
9
9
SU_DEL
Input Data Valid After DQS
Input
Input Data Hold After DQS
Input
Output Data Invalid Before
DQS Output
Output Data Invalid After DQS
Output
MEM LPDDR Serial Data
Speed
SCLK Frequency
LPDDR Data Transfer Rate
Input Data Valid After DQS
Input
Input Data Hold After DQS
Input
Output Data Invalid Before
DQS Output
Output Data Invalid After DQS
Output
MEM DDR Serial Data Speed
SCLK Frequency
MEM DDR Data Transfer Rate
Input Data Valid After DQS
Input
Input Data Hold After DQS
Input
Output Data Invalid Before
DQS Output
Output Data Invalid After DQS
Output
MEM DDR Serial Data Speed
SCLK Frequency
MEM DDR2 Data Transfer
Rate
and t
H_DEL
Description
values use the SCLK_ZERHOLD default step size. Each step is 105ps (-6), 113ps (-5), 120ps (-4).
SU
= t
HO
= (t
DVE
- t
DVA
MachXO2-1200/U and
larger devices, right
side only.
MachXO2-1200/U and
larger devices, right
side only.
MachXO2-1200/U and
larger devices, right
side only.
- 0.03ns)/2.
Device
3-22
0.529
0.545
0.555
Min.
0.25
0.25
0.25
0.25
0.25
0.25
N/A
N/A
0
-6
DC and Switching Characteristics
0.369
0.350
0.360
Max.
280
140
280
300
150
300
300
150
300
MachXO2 Family Data Sheet
0.530
0.538
0.549
Min.
0.25
0.25
0.25
0.25
0.25
0.25
N/A
N/A
0
-5
0.395
0.387
0.378
Max.
250
125
250
250
125
250
250
125
250
0.527
0.532
0.542
Min.
0.25
0.25
0.25
0.25
0.25
0.25
N/A
N/A
0
-4
0.421
0.414
0.406
Max.
208
208
208
208
104
208
104
208
104
Units
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI

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