IS25LQ016-JKLE-TR ISSI, IS25LQ016-JKLE-TR Datasheet
IS25LQ016-JKLE-TR
Specifications of IS25LQ016-JKLE-TR
Related parts for IS25LQ016-JKLE-TR
IS25LQ016-JKLE-TR Summary of contents
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... Chip Erase 5s (Typ) GENERAL DESCRIPTION The IS25LQ016 are 16 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad- output. The devices are designed to support a 50 MHz fclock rate in normal read mode, and 104 MHz in fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power supply, ranging from 2 ...
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... CONNECTION DIAGRAMS CE (IO1) 2 WP# (IO2 GND 5 4 8-Pin SOIC/VSOP Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 Vcc CE (IO1) HOLD# (IO3) 3 WP# (IO2) SCK 4 GND ) SI (IO0 8-pin WSON IS25LQ016 Vcc 8 7 HOLD#(IO3) SCK (IO0 2 ...
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... Hold: Pause serial communication by the master device without resetting (IO3) the serial sequence. When the QE bit of Status Register-2 is set for “1”, the function is Serial Data Input & Output (for 4xI/O read mode) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 3 ...
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... BLOCK DIAGRAM WP# (IO2) SI (IO0) SO (IO1) HOLD# (IO3) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 4 ...
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... SPI MODES DESCRIPTION Multiple IS25LQ016 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) ...
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... Configuration Register: 1. Configurable sector size: The memory array of IS25LQ016 is divided into uniform 4 KByte sectors or uniform 64 KByte blocks (a block consists of sixteen adjacent sectors). Table 1 illustrates the memory map of the devices. ...
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... BLOCK/SECTOR ADDRESSES Table 1. Block/Sector Addresses of IS25LQ016 Block No. Memory Density (64Kbyte) Block 0 Block 1 : Block 7 Block 8 16Mbit : : Block 15 Block Block 31 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 Sector Sector No. Size (KBytes) Sector 0 4 000000h - 000FFFh Sector 1 4 001000h - 001FFFh : : Sector 15 4 00F000h - 00FFFFh ...
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... SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground. Bit 6 Bit 5 Bit 4 Bit 3 QE BP3 BP2 BP1 IS25LQ016 ), the bits of Status Register IL ), the Status Register IH Bit 2 Bit 1 Bit 0 BP0 WEL WIP ...
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... Quad output function enable Status Register Write Disable: (See Table 10 for details) Bit 7 SRWD "0" indicates the Status Register is not write-protected (default) "1" indicates the Status Register is write-protected Table 9. Block Write Protect Bits for IS25LQ016C Status Register Bits BP3 BP2 BP1 0 ...
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... IL Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 The IS25LQ016 also provides two software write protection features: a. Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled first, the program, erase or write register instruction will be ignored ...
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... Read 65 bytes of Security area Raw HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25LQ016. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. Integrated Silicon Solution, Inc.- www.issi.com Rev ...
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... BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle Table 12. Product Identification Product Identification Manufacturer ID Device ID: IS25LQ016C Dummy Bytes Device ID1 IS25LQ016 time duration. If the RES1 Data First Byte Second Byte Device ID1 Device ID2 14h ...
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... Rev. 0A 2/1/2013 by the first Device ID1 (14h) and the Device ID 2(45h), in the case of the IS25LQ016C), each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high ...
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... ID (7Fh). The manufacture and device ID can be read continuously, alternating from one to the others. The instruction is completed by driving CE# high Data Out2 IS25LQ016 ... 3 - BYTE ADDRESS ... ...
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... ADDRESS will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh) ADDRESS will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 15 ...
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... WRITE ENABLE OPERATION The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the IS25LQ016 is reset to the write –protected state after power-up. The WEL bit must be write enabled before any write operation, including sector, block erase, chip Figure 6 ...
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... Figure 9. Write Status Register Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of Status Register. or “1”s into the non-volatile BP3, BP2, BP1, BP0 and SRWD bits ...
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... DEVICE OPERATION (CONTINUED) READ COMMAND (READ DATA) OPERATION The Read Data (READ) instruction is used to read memory data of a IS25LQ016under normal mode running up to 50MHz. The READ instruction code is transmitted via the Sl line, followed by three address bytes (A23 - A0) of the first memory location to be read. A total of 24 address ...
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... FAST_READ instruction. The FAST_READ instruction is terminated by driving CE# high ( Fast Read Data instruction is issued while IH , during the an Erase, Program or Write cycle is in process (BUSY=1) CT the instruction is ignored and will not have any effects on the current cycle IS25LQ016 19 ...
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... BYTE ADDRESS DATA OUT IS25LQ016 ). If a FRDO ... ... DATA OUT ...
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... DATA OUT IS25LQ016 ... 3 - BYTE ADDRESS MODE BITS ... ... ...
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... FRQO instruction. FRQO instruction is terminated by driving CE# high (V instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle IS25LQ016 ...
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... BYTE ADDRESS DATA OUT 1 DATA OUT IS25LQ016 ... ... DATA OUT ...
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... The first bit (MSb) is output on IO3, while simultaneously the second bit is output on IO2, the Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 third bit is output on IO1, etc. Figure 18 illustrates the timing sequence. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out ...
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... DATA OUT 2 DATA OUT 3 DATA OUT IS25LQ016 BYTE ADDRESS MODE BITS ...
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... The timing sequence is different depending whether the MR command is used after an FRDIO or FRQIO, as shown in Figure 20. Quad I INSTRUCTION = 1111 1111b IS25LQ016 DATA OUT 1 DATA OUT 2 Mode Reset for Dual I ...
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... Figure 21. Page Program Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “ ...
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... IO2 IO3 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 BYTE ADDRESS 00110010b DATA IS25LQ016 ... ... 0 29 ...
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... BLOCK_ER COMMAND (BLOCK ERASE) OPERATION A Block Erase (BLOCK_ER) instruction erases a 64 Kbyte block of the IS25LQ016. Before the execution of a BLOCK_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation. ...
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... DEVICE OPERATION (CONTINUED) Figure 22. Sector Erase Sequence Figure 23. Block Erase Sequence Figure 24. Chip Erase Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 31 ...
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... The SIR protection bit is in the address 000100h. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 MSB Data Byte 2 IS25LQ016 ) is initiated. While the potp ... ... 24-bit address 42 43 ... ... 6 5 Data Byte n 32 ...
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... Byte1 Byte2 X X Bit 1~bit 7 do not care Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 Byte255 IS25LQ016 OTP control byte Byte256 Bit 0 When bit the 256 OTP bytes become read only 33 ...
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... MSB 24-bit address 46 47 ... ... Data output N Data output 2 IS25LQ016 th ) byte keeps being read on the SO pin Data Out0 ...
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... 130 2 2.3V < V < 3. -100 A OH IS25LQ016 o C IS25LQ016 105 - - - 105 - 125 C 2.3 V – 3 ...
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... Output Disable Time DIS Sector Erase Time Block Erase Time(64Kbyte Chip Erase Time (16Mb) t Page Program Time PP t res1 Write Status Register time w Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 = 2 3 Min Typ 0.5 5 ...
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... AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING Note: 1. For SPI Mode 0 (0,0) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 (1) IS25LQ016 37 ...
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... PIN CAPACITANCE ( MHz 25°C ) Typ OUT Note: These parameters are characterized but not 100% tested. OUTPUT TEST LOAD 30pf Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 Max Units INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL IS25LQ016 Conditions OUT 38 ...
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... At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. All Write Commands are Rejected tVCE tPUW Parameter IS25LQ016 Read Access Allowed Device fully accessible Time Min. Max. Unit 10 us ...
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... From writing erase command to erase completion 0.5 0.7 From writing program command to program completion 10 Min Typ Unit 100,000 Cycles 20 Years 2,000 Volts 200 Volts 100 + I mA CC1 IS25LQ016 Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78 40 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JB 8-Pin SOIC 208mil Broad Small Outline Integrated Circuit Package (Unit : millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 41 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JK 8-pin WSON Ultra-Thin Small Outline No-Lead Package (Unit : millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 42 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JF 8-Pin 208mil VSOP Package (Unit : millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 43 ...
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... Safe Guard function is a security function for customer to protect by sector (4Kbyte). Every sector has one bit register to decide it will under safe guard protect or not. (“0”means protect and “1” means not protect by safe guard.) IS25LQ016 (sector 0~sector 511) Mapping table for safe guard register ...
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... Fig c. shows the complete steps for program safe guard register. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 ) after the data comes out A23-A0 IS25LQ016 byte st 1 byte D7-D0 D7-D0 ...
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... A23- SCK SI AAh A23- SCK SI 80h A23- SCK SI AAh A23- SCK SI 2Bh Fig b. Erase safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 46 ...
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... SCK SI 55h SCK SI 23h Fig c. program safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 31 32 A23- A23- A23- A23- byte 2nd byte A23-A0 D7-D0 D7-D0 IS25LQ016 ...
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... A0 through A11 are not decoded. The remaining sectors within the same block remain in read-only mode 26h A23-A16 IS25LQ016 Command Cycle 4 Bytes 1 Byte A15-A8 A7-A0 Maximum Frequency 100 MHz ...
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... Sector Unlock command. The instruction code does not require an address to be specified, as only Figure e. Sector Lock Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 one sector can be enabled at a time. The remaining sectors within the same block remain in read-only mode. 49 ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 2/1/2013 IS25LQ016 50 ...
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... SOIC 150mil IS25LQ016-JKLE 8-pin WSON (Call Factory) IS25LQ016-JVLE 8-pin VVSOP 150mil IS25LQ016-JMA* 16-pin SOIC 300mil (Call Factory) IS25LQ016-JBA* 8-pin SOIC 208mil (Call Factory) IS25LQ016-JNA* 8-pin SOIC 150mil (Call Factory) IS25LQ016-JKA* 8-pin WSON (Call Factory) IS25LQ016-JVA* 8-pin VVSOP 150mil (Call Factory) IS25LQ016 51 ...