IS25LQ016-JKLE-TR ISSI, IS25LQ016-JKLE-TR Datasheet - Page 21

• Manufacturer Part Number: IS25LQ016-JKLE-TR
• Description: Flash 16M 2.3-3.6V 104Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LQ016-JKLE-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 16 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8
• Organization: 2048 K x 8

DEVICE OPERATION (CONTINUED)
FRDIO COMMAND (FAST READ DUAL I/O) OPERATION
The FRDIO instruction is similar to the FRDO
instruction, but allows the address bits to be input two
bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
The FRDIO instruction code is followed by three
address bytes (A23 – A0) and a mode byte,
transmitted via the IO0 and IO1 lines, with each pair of
bits latched-in during the rising edge of SCK. The
address MSb is input on IO1, the next bit on IO0, and
continues to shift in alternating on the two lines. The
mode byte contains the value Ax, where x is a “don’t
care” value. Then the first data byte addressed is
shifted out on the IO1 and IO0 lines, with each pair of
bits shifted out at a maximum frequency f
falling edge of SCK. The MSb is output on IO1, while
simultaneously the second bit is output on IO0. Figure
15 illustrates the timing sequence.
Figure 15. Fast Read Dual I/O Sequence (with command decode cycles)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
2/1/2013
CE#
SCK
SCK
CE#
IO0
IO1
IO0
IO1
22
23
6
7
24
DATA OUT 1
0
INSTRUCTION = 1011 1011b
5
4
25
1
3
2
26
2
0
1
27
3
6
CT
7
28
4
DATA OUT 2
, during the
5
4
29
5
2
3
30
6
1
0
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDIO instruction. FRDIO
instruction is terminated by driving CE# high (V
The device expects the next operation will be another
FRDIO. It remains in this mode until it receives a
Mode Reset (FFh) command. In subsequent FRDIO
execution, the command code is not input, saving
timing cycles as described in Figure 16. If a FRDIO
instruction is issued while an Erase, Program or Write
cycle is in process (BUSY=1) the instruction is ignored
and will not have any effects on the current cycle
31
7
7
6
22
23
8
3 - BYTE ADDRESS
22
21
9
20
10
19
11
...
...
...
18
2
3
IS25LQ016
0
1
19
MODE BITS
20
6
7
21
5
4
IH
).
21