IS25LQ016-JKLE-TR ISSI, IS25LQ016-JKLE-TR Datasheet - Page 30

• Manufacturer Part Number: IS25LQ016-JKLE-TR
• Description: Flash 16M 2.3-3.6V 104Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LQ016-JKLE-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 16 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8
• Organization: 2048 K x 8

DEVICE OPERATION (CONTINUED)
ERASE OPERATION
The memory array of the IS25LQ016 is organized into
uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (a
block consists of sixteen adjacent sectors).
Before a byte can be reprogrammed, the sector or
block that contains the byte must be erased (erasing
sets bits to “1”). In order to erase the devices, there are
three erase instructions available: Sector Erase
(SECTOR_ER), Block Erase (BLOCK_ER) and Chip
Erase (CHIP_ER). A sector erase operation allows any
individual sector to be erased without affecting the data
in other sectors. A block erase operation erases any
individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block
erase or chip erase operation can be executed prior to
any programming operation.
SECTOR_ER COMMAND (SECTOR ERASE)
OPERATION
A SECTOR_ER instruction erases a 4 Kbyte sector
Before the execution of a SECTOR_ER instruction, the
Write Enable Latch (WEL) must be set via a Write
Enable (WREN) instruction. The WEL bit is reset
automatically after the completion of sector an erase
operation.
A SECTOR_ER instruction is entered, after CE# is
pulled low to select the device and stays low during the
entire instruction sequence The SECTOR_ER
instruction code, and three address bytes are input via
SI. Erase operation will start immediately after CE# is
pulled high. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
22 for Sector Erase Sequence.
During an erase operation, all instruction will be
ignored except the Read Status Register (RDSR)
instruction. The progress or completion of the erase
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
2/1/2013
operation can be determined by reading the WIP bit in
the Status Register using a RDSR instruction. If the
WIP bit is “1”, the erase operation is still in progress. If
the WIP bit is “0”, the erase operation has been
completed.
BLOCK_ER COMMAND (BLOCK ERASE)
OPERATION
A Block Erase (BLOCK_ER) instruction erases a 64
Kbyte block of the IS25LQ016. Before the execution of
a BLOCK_ER instruction, the Write Enable Latch
(WEL) must be set via a Write Enable (WREN)
instruction. The WEL is reset automatically after the
completion of a block erase operation.
The BLOCK_ER instruction code and three address
bytes are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the
BLOCK_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 23 for Block Erase
Sequence.
CHIP_ER COMMAND (CHIP ERASE) OPERATION
A Chip Erase (CHIP_ER) instruction erases the entire
memory array of a IS25LQ016. Before the execution of
CHIP_ER instruction, the Write Enable Latch (WEL)
must be set via a Write Enable (WREN) instruction.
The WEL is reset automatically after completion of a
chip erase operation.
The CHIP_ER instruction code is input via the SI.
Erase operation will start immediately after CE# is
pulled high, otherwise the CHIP_ER instruction will not
be executed. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
24 for Chip Erase Sequence.
IS25LQ016
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