IS25LQ016-JKLE-TR ISSI, IS25LQ016-JKLE-TR Datasheet - Page 24

• Manufacturer Part Number: IS25LQ016-JKLE-TR
• Description: Flash 16M 2.3-3.6V 104Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LQ016-JKLE-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 16 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8
• Organization: 2048 K x 8

DEVICE OPERATION (CONTINUED)
FRQIO COMMAND (FAST READ QUAD I/O) OPERATION
The FRQIO instruction is similar to the FRQO
instruction, but allows the address bits to be input four
bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
The FRQIO instruction code is followed by three
address bytes (A23 – A0) and a mode byte,
transmitted via the IO3, IO2, IO0 and IO1 lines, with
each group of four bits latched-in during the rising edge
of SCK. The address MSb is input on IO3, the next bit
on IO2, the next bit on IO1, the next bit on IO0, and
continue to shift in alternating on the four. The mode
byte contains the value Ax, where x is a “don’t care”
value. After four dummy clocks, the first data byte
addressed is shifted out on the IO3, IO2, IO1 and IO0
lines, with each group of four bits shifted out at a
maximum frequency f
The first bit (MSb) is output on IO3, while
simultaneously the second bit is output on IO2, the
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
2/1/2013
CT
, during the falling edge of SCK.
third bit is output on IO1, etc. Figure 18 illustrates the
timing sequence.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRQIO instruction. FRQIO
instruction is terminated by driving CE# high (V
The device expects the next operation will be another
FRQIO. It remains in this mode until it receives a
Mode Reset (FFh) command. In subsequent FRDIO
execution, the command code is not input, saving
cycles as described in Figure 19. If a FRQIO instruction
is issued while an Erase, Program or Write cycle is in
process (BUSY=1) the instruction is ignored and will not
have any effects on the current cycle
IS25LQ016
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