IS25LQ016-JKLE-TR ISSI, IS25LQ016-JKLE-TR Datasheet - Page 10

• Manufacturer Part Number: IS25LQ016-JKLE-TR
• Description: Flash 16M 2.3-3.6V 104Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LQ016-JKLE-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 16 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8
• Organization: 2048 K x 8

REGISTERS (CONTINUED)
PROTECTION MODE
The IS25LQ016 have two types of write-protection
mechanisms: hardware and software. These are
used to prevent irrelevant operation in a possibly
noisy environment and protect the data integrity.
HARDWARE WRITE-PROTECTION
The devices provide two hardware write-protection
features:
a. When inputting a program, erase or write status
register instruction, the number of clock pulse is
checked to determine whether it is a multiple of
eight before the executing. Any incomplete
instruction command sequence will be ignored.
b. Write inhibit is 2.0V, all write sequence will be
ignored when Vcc drop to 2.0V and lower.
c. The Write Protection (WP#) pin provides a
hardware write protection method for BP3, BP2,
BP1, BP0 and SRWD in the Status Register. Refer
to the STATUS REGISTER description.
SOFTWARE WRITE PROTECTION
DEVICE OPERATION
The IS25LQ016 utilize an 8-bit instruction register.
Refer to Table 11 Instruction Set for details of the
Instructions and Instruction Codes. All instructions,
addresses, and data are shifted in with the most
significant bit (MSB) first on Serial Data Input (SI). The
input data on SI is latched on the rising edge of Serial
Clock (SCK) after Chip Enable (CE#) is driven low
(V
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
2/1/2013
IL
). Every instruction sequence starts with a one-byte
instruction code and is followed by address bytes, data
bytes, or both address bytes and data bytes,
depending on the type of instruction. CE# must be
driven high (V
sequence has been shifted in.
The timing for each instruction is illustrated in the
following operational descriptions.
The IS25LQ016 also provides two software write
protection features:
a. Before the execution of any program, erase or
write status register instruction, the Write Enable
Latch (WEL) bit must be enabled by executing a
Write Enable (WREN) instruction. If the WEL bit is
not enabled first, the program, erase or write
register instruction will be ignored.
b. The Block Protection (BP3, BP2, BP1, BP0) bits
allow part or the whole memory area to be write-
protected.
Table 10. Hardware Write Protection on Status
Register
SRWD
0
1
0
1
IH
) after the last bit of the instruction
WP#
High
High
Low
Low
IS25LQ016
Status Register
Protected
Writable
Writable
Writable
10