AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 159

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

20. Dual Analog Comparators
Figure 20-1. Dual Comparator Block Diagram
3714A–MICRO–7/11
(P2.7) AIN3
(P2.6) AIN2
(P2.5) AIN1
(P2.4) AIN0
The AT89LP51RD2/ED2/ID2 provides two analog comparators. The analog comparators have
the following features:
A block diagram of the dual analog comparators with relevant connections is shown in
20-1. Input options allow the comparators to function in a number of different configurations as
shown in
tive input is greater than the negative input. Otherwise the output is a zero. Setting the CENA
(ACSRA.3) and CENB (ACSRB.3) bits enable Comparator A and B respectively. The user must
also set the CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the comparator inputs
before using a comparator. When a comparator is first enabled, the comparator output and inter-
rupt flag are not guaranteed to be stable for 10 µs. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt flag must be cleared before
the interrupt is enabled in order to prevent an immediate interrupt service.
Before enabling the comparators, the analog inputs should be tristated by putting P2.4, P2.5,
P2.6 and P2.7 into input-only mode. See
to use the Analog Comparators with external program memory or external data memory with 16-
bit addresses (MOVX @DPTR) since these functions require the use of Port 2 for addressing.
• Internal 3-level Voltage Reference (1.125V, 1.25V, 1.375V)
• Four Shared Analog Input Channels
• Selectable Interrupt Conditions
• Hardware Debouncing Modes
– Configure as Multiple Input Window Comparator
– High- or Low-level
– Rising- or Falling-edge
– Output Toggle
Figure
CSB1
CSA1
CSB0
CSA0
11
10
01
00
00
01
10
11
20-4. Comparator operation is such that the output is a logic “1” when the posi-
AT89LP51RD2/ED2/ID2 Preliminary
11
10
01
00
00
01
10
11
RFB1
RFA1
RFB0
RFA0
B
A
“Port Analog Functions” on page
V
V
V
AREF+Δ
AREF
AREF-Δ
CMB2
CMB1
CMB0
CMA2
CMA1
CMA0
CFB
CFA
CMPB
CMPA
ECMP
74. It is not possible
Interrupt
Figure
159