AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 161

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

20.2
20.3
3714A–MICRO–7/11
Internal Reference Voltage
Comparator Interrupt Debouncing
The negative input terminal of each comparator may be connected to an internal voltage refer-
ence by changing the RFB
set to 1.25 V ±5%. The voltage reference also provides two additional voltage levels approxi-
mately 125 mV above and below V
as an internally referenced window comparator with up to four input channels. Changing the ref-
erence input must follow the same routine used for changing the positive input as described in
“Analog Input Muxes”
The comparator output is normally sampled every clock cycle. The conditions on the analog
inputs may be such that the comparator output will toggle excessively. This is especially true if
applying slow moving analog inputs. Three debouncing modes are provided to filter out this
noise for edge-triggered interrupts. In debouncing mode, the comparator uses Timer 1 to modu-
late its sampling time when CxC
waits until two Timer 1 overflows have occurred before resampling the output. If the new sample
agrees with the expected value, CFx is set. Otherwise, the event is ignored. The filter may be
tuned by adjusting the time-out period of Timer 1. Because Timer 1 is free running, the
debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out
period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out
periods later. See
flows, i.e. CxC
be accepted as an edge event.
Figure 20-3. Negative Edge with Debouncing Example
When the comparator sampling clock is configured for a timer overflow, Timer 1 still controls the
debouncing. The sampling clock will determine when the edge event occurs and the interrupt will
be validated two Timer 1 overflows after this event. When Timer 1 is selected for the sampling
clock, this means the interrupt will occur on the second overflow after the overflow that sampled
desired event.
Timer 1 Overflow
Comparator Out
1-0
!= 00B, any change in the comparator output must be valid after 4 samples to
Figure
CFx
above.
Start
20-3. When the comparator clock is provided by one of the timer over-
1-0
AT89LP51RD2/ED2/ID2 Preliminary
or RFA
1-0
AREF
= 00B. When a relevant transition occurs, the comparator
1-0
. These levels may be used to configure the comparators
bits in AREF. The internal reference voltage, V
(rejected)
Compare
Start
(accepted)
Compare
AREF
161
, is