ISL1902FAZ-T7A Intersil, ISL1902FAZ-T7A Datasheet
ISL1902FAZ-T7A
Specifications of ISL1902FAZ-T7A
Related parts for ISL1902FAZ-T7A
ISL1902FAZ-T7A Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. 130 180 ...
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Pin Configuration Pin Descriptions PIN # SYMBOL 1 VDD VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. 2 ...
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... OUT has pull-down capability when UVLO is active or when the IC is not biased. DD Ordering Information PART NUMBER (Notes ISL1902FAZ ISL 1902FAZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Functional Block Diagram - ISL1902 VREF Bias and VDD Reference Generator UVLO + - OTP Shutdown BG 150 - 170 °C GND BIAS/UVLO/OTP DUTY CYCLE TO VOLTAGE LPOUT CONVERTER LOW PASS FILTER Master CLK Oscillator No AC Counter CLK Peak ...
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Typical Application - SEPIC Topology with PWM Dimming and Ambient Light Compensation DIMMER EMI AC FILTER MAINS 1 OUT 24 VDD 2 PRELOAD PWMOUT 23 3 OFFREF INRUSH 22 4 VREF GND 21 5 IOUT CS+ OVP ...
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Typical Application - Isolated Flyback with PWM Dimming and Ambient Light Compensation DIMMER EMI AC FILTER MAINS 1 OUT 16 VDD 2 OFFREF PWMOUT VREF DHC 4 GND 13 IOUT ISL1904 5 CS ...
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Typical Application - Non-Isolated Flyback with PWM Dimming and Ambient Light Compensation DIMMER EMI AC FILTER MAINS 1 OUT 24 VDD 2 PRELOAD PWMOUT OFFREF INRUSH 4 GND 21 VREF 5 20 IOUT AC 6 CS+ OVP ...
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... Lead QSOP (Notes 0.3V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C REF + 0.3V Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C REF Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Supply Voltage Range (Typical 9VDC to 20VDC , = 17V 54kΩ C ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to the Block Diagram on page 4 and Typical Application schematics starting on page 5. V Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER PULSE WIDTH ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to the Block Diagram on page 4 and Typical Application schematics starting on page 5. V Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER Clamp Voltage ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to the Block Diagram on page 4 and Typical Application schematics starting on page 5. V Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER Operating Range ...
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Typical Performance Curves 1.001 1.000 0.999 0.998 0.997 0.996 -40 -25 - TEMPERATURE (°C) FIGURE 3. REFERENCE VOLTAGE vs TEMPERATURE 2.5 2.0 1.5 1.0 0 100 125 DELAY RESISTANCE (kΩ) FIGURE ...
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Test Waveforms and Circuits OC THRESHOLD OC LEADING EDGE BLANKING OC PROPAGATION DELAY OC + LEB TO OUT DELAY OUT FIGURE 9. OC +LEB TO OUT DELAY 13 ISL1902 (Continued) AC MAINS INRUSH Ω 5k 54k VDD 1 VDD 2 ...
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Functional Description Features The ISL1902 LED driver is an excellent choice for low cost, AC mains powered single conversion LED lighting applications. It provides active power factor correction (PFC) to achieve high power factor using critical conduction mode operation, and ...
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The first calculation required is to determine the required secondary inductance. 2 ⋅ – o max ------------------------------------------- - ⋅ ⋅ typ avg o The turns ratio ...
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AC voltage waveform at the lowest RMS input voltage. Therefore, the lowest DC or equivalent DC (RMS) input voltage is used as the design point with a corresponding selection of a minimum desired operating frequency. During the ...
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WINDING CURRENT FET D-S VOLTAGE FIGURE 14. QUASI-RESONANT NEAR-ZVS SWITCHING The delay duration is set with a resistor from DELADJ to ground. Figure 5 on page 12 presents the graphical relationship between the delay duration and the value of the ...
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EM I FILTE R ISL1902 FIGURE 18. ALTERNATE AC DETECTION The advantage to sensing the AC voltage directly, rather than the rectified voltage, is that there is no error in detecting the AC zero crossing. If ...
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VREF AC 20 PWM CONTROL 5 19 LOUT 6 18 REFIN LREF 8 17 LPOUT LFB ISL1902 13 FIGURE 22. ALTERNATE METHOD FOR USING PWM INPUT CONTROL WITH AN AMBIENT ...
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The red trace is the current source supplying the output. The blue trace is the output capacitor voltage. The green trace is the LED current. When the PWM signal is off, the 50mA current source charges C and the output ...
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FIN LPO U T LFB ISL1902 12 FIGURE 28. SECOND LED STRING CONTROL The linear amplifier may also be used ...
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R S CS+ DIFFERENTIAL IOUT CS - IOUT PROCESSOR CS- REFERENCE AC LPOUT GENERATOR + REFIN VERR EA1 _ FB1 EA2 _ VREF FB2 R ISL1902 C FB2 C FB1 FIGURE 30. CONTROL LOOP CONFIGURATION In ...
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PRELOAD Signal PRELOAD is a digital signal used to control an external FET that discharges the output capacitance low for more than ~30ms REFIN drops below the OFFREF threshold. This feature prevents the output capacitor ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...
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Package Outline Drawing M24.15 24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (QSOP/SSOP) 0.150” WIDE BODY Rev 3, 2/13 3 -A- 8.74 8.55 0.635 BSC 0.30 SIDE VIEW 1 7 0.20 0.17(0.007 7.11 5.59 4.06 0.635 TYPICAL RECOMMENDED ...