ISL61862BIRZ-T Intersil, ISL61862BIRZ-T Datasheet
ISL61862BIRZ-T
Specifications of ISL61862BIRZ-T
Related parts for ISL61862BIRZ-T
ISL61862BIRZ-T Summary of contents
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... USB PORT_2 0.7 -40 FIGURE 2. NORMALIZED r CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. - TEMPERATURE (° ...
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Simplified Block Diagram GND VIN VIN EN Pin Configurations ISL6186 (8 LD SOIC/DFN) TOP VIEW GND 1 (GND) VIN 2 EPAD DFN ONLY 3 VIN 4 EN/EN Pin Descriptions PIN NUMBER 8 Ld SOIC/DFN 10 Ld DFN SYMBOL 1 1 ...
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Pin Descriptions (Continued) PIN NUMBER 8 Ld SOIC/DFN 10 Ld DFN SYMBOL 5 6 FLT OUT - 10 PGD PD PD EPAD (DFN only) Ordering Information PART NUMBER PART EN/EN (Notes ...
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... EN ISL61861BIBZ 61861B IBZ EN ISL61861CIBZ 61861C IBZ EN ISL61861DIBZ 61861D IBZ EN ISL61861EIBZ 61861E IBZ EN ISL61861FIBZ 61861F IBZ EN ISL61861GIBZ 61861G IBZ EN ISL61861HIBZ 61861H IBZ EN ISL61862AIRZ 62AI EN ISL61862BIRZ 62BI EN ISL61862CIRZ 62CI EN ISL61862DIRZ 62DI EN ISL61862EIRZ 62EI EN ISL61862FIRZ 62FI EN ISL61862GIRZ 62GI EN ISL61862HIRZ 62HI EN ISL61863AIRZ 63AI EN ISL61863BIRZ 63BI ...
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... Lead 3x3 DFN Package (Notes Lead 3x3 DFN Package (Notes Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = 5V Unless Otherwise Specified. Boldface limits apply over the operating temperature IN ...
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Electrical Specifications V range, 0°C to +75°C or -40°C to +85°C . SYMBOL PARAMETER I Trip Current TRIP_5 IN I TRIP_5 I TRIP_5 I Trip Current 3.3V TRIP_3 IN I TRIP_3 I TRIP_3 I Trip ...
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Electrical Specifications V range, 0°C to +75°C or -40°C to +85°C . SYMBOL PARAMETER Ren_h ENABLE Pull-Down Resistor Ren_l ENABLE Pull-Up Resistor t Enable to Output Turn-on Time ON t Enable to Output Turn-off Time OFF t Enable to Power ...
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Functional Description Power On Reset (POR) The ISL6186 POR feature inhibits device functionality when V <V . UVLO Reverse Polarity Protection In any event in which the power switch is disabled or powered down, and V > there ...
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Typical Performance Curves 3 TRIP 2.5 3.3V I TRIP 5V I 2.0 sc 2.5V I TRIP 5V I LIM 1.5 2.5V I LIM 3. 1.0 -40 25 TEMPERATURE (°C) FIGURE 5. 1.5A CONTINUOUS CURRENT CHARACTERISTICS 4.5 ...
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Typical Performance Curves FIGURE 11. 1.5A VARIANT I LIM FAULT PG FIGURE 13. 3.6A VARIANT I WAVEFORM w PG LIM EN C =10µF L FIGURE 15. V TURN-ON/RISE TIME vs C OUT R = 10Ω ISL6186 (Continued) EN ...
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Typical Performance Curves 3A VARIANT 78A/ms 16A/ms 1.6A/ 2.75A LOAD FIGURE 17. OC RAMP RATE I LIM 3A VARIANT FIGURE 19. TURN-ON INTO AN OVERCURRENT FIGURE 21. OVERCURRENT RETRY FUNCTION 11 ISL6186 (Continued) 3A VARIANT 0.5A OC 300µs ...
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Typical Performance Curves FIGURE 23 2.4V TURN-ON INTO 0.88Ω IN Test Circuits + 10k FLT 5V VIN OUT ISL6186 V/(V /10Ω) DS(ON) OUT FIGURE 25A. r DS(ON) 10k FLT 5V VIN OUT ISL6186 0-V EN ...
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ISL61863EVAL1Z Schematic and Photo * NOTE: *PGD Output only available on ISL61863 types FIGURE 28A. ISL61863EVAL1Z SCHEMATIC FIGURE 28. ISL61863EVAL1Z SCHEMATIC and ISL61863EVAL1Z PHOTOGRAPH Application Information Using the ISL6186XEVAL1Z Platform General and Biasing Information There are three evaluation platforms for ...
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... FLT Output Pull-up Resistor R3 PGD Output Pull-up Resistor * only on ISL61863EVAL1Z C1 Decoupling Capacitor C2 Load Capacitor 14 ISL6186 COMPONENT FUNCTION Intersil, ISL6186 5.1Ω, 5%, 3W 10kΩ, 0805 10kΩ, 0805 2.2µF on ISL61862EVAL1Z 33µF on ISL61861EVAL1Z and ISL61863EVAL1Z 10µF 16V Electrolytic, Radial Lead COMPONENT DESCRIPTION FN7698.2 November 3, 2011 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...
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Package Outline Drawing L8.3x3J 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0 9/09 3.00 (4X) 0.15 6 PIN 1 INDEX AREA TOP VIEW ( 2. 1.95) (1.64) ( 2.80 ) PIN 1 (6x 0.65) TYPICAL RECOMMENDED LAND ...
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Package Outline Drawing L10.3x3 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09 3.00 6 PIN 1 INDEX AREA (4X) 0.10 TOP VIEW PACKAGE OUTLINE (10 x 0.55) (10x 0.23) (8x 0.50) 1.60 TYPICAL RECOMMENDED LAND PATTERN 17 ISL6186 A ...
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Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/11 INDEX AREA TOP VIEW 5.00 (0.197) 4.80 (0.189) 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 18 ISL6186 DETAIL "A" 6.20 (0.244) 5.80 ...