IS43R16160B-5TL ISSI, Integrated Silicon Solution Inc, IS43R16160B-5TL Datasheet

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... IS43R83200B IS43R16160B, IC43R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM FEATURES: • 2.5V+0.2V (-5, -6, -75) dd ddq • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK) • ...

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... IS43R83200B IS43R16160B, IC43R16160B PIN CONFIGURATION Package Code B: 60-ball FBGA (top view) (8mm x 13mm Body, 0.8mm x 1.0mm Ball Pitch) Top View (Balls seen through the package) UDQS LDQS UDM LDM CLK WE A12 RAS PIN DESCRIPTION: for x16 A0-A12 Row Address Input A0-A8 ...

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... IS43R83200B IS43R16160B, IC43R16160B PIN CONFIGURATIONS 66 pin TSOP - Type II for x8, x16 x8 x16 V DD DQ0 DQ0 DQ1 DQ1 DQ2 DQ3 DQ2 DQ4 DQ5 DQ3 DQ6 DQ7 DDQ NC LDQS NC V VDD DD DNU DNU NC LDM WE CAS CAS RAS RAS CS NC BA0 BA0 BA1 BA1 A10/AP ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I PIN FUNCTION SYMBOL TYPE CLK, /CLK Input CKE Input /CS Input /RAS, /CAS, /WE Input A0-12 Input BA0,1 Input DQ0-7 (x8), Input / Output DQ0-15 (x16), DQS (x8) Input / Output UDQS, LDQS (x16) DM (x8) Input UDM, LDM (x16 Power Supply DD SS ...

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... IS43R83200B IS43R16160B, IC43R16160B BLOCK DIAGRAM x8 DLL Memory Arra Mode Re gister Addres s B uffer A0 0,1 Integrated Silicon Solution, Inc. Rev. B 10/31/ I/O B uffer ffer Memory Memory Arra y Arra Control C ircu itry Control Signal B uffer Cl ock B uffer /CS /RAS /CAS CLK /CLK CKE DQ S Memory ...

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... IS43R83200B IS43R16160B, IC43R16160B BLOCK DIAGRAM x16 DLL Memory Array Bank #0 Mode Re gister Addres s B uffer A0 0 UDQS I/O B uffer DQ S Buffer Memory Memory Array Array Control C ircu itry Control Signal B uffer Cl ock B uffer /CS /RAS /CAS CLK /CLK CKE Memory Array /WE UDM , LD M Integrated Silicon Solution, Inc ...

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... Preliminary IS43R83200B Preliminary IS43R16160B, IC43R16160B BASIC FUNCTIONS ISSI's 256-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS , CKE and A10 are used as chip select, refresh option, and precharge option, respectively ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B I I COMMAND TRUTH TABLE COMMAND MNEMONIC DESEL Deselect NOP No Operation Row Address Entry & ACT Bank Activate PRE Single Bank Precharge PREA Precharge All Banks Column Address Entry WRITE & Write Column Address Entry & Write with ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B FUNCTION TRUTH TABLE Current State /CS /RAS /CAS /WE Address IDLE BA, CA, A10 BA BA, A10 ROW ACTIVE BA, CA, A10 BA, CA, A10 BA BA, A10 READ(Auto- Precharge Disabled BA, CA, A10 BA, CA, A10 BA BA, A10 Integrated Silicon Solution, Inc. DDR SDRAM (Rev.1.1) Rev ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address WRITE(Auto- Precharge Disabled READ with Auto-Precharge WRITE with Auto-Precharge DDR SDRAM (Rev.1.1) 256M Double Data Rate Synchronous DRAM Command X X DESEL H X NOP L BA TERM H BA, CA, A10 ...

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... Preliminary Preliminary IS43R83200B IS43R16160B, IC43R16160B FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address PRE- CHARGING BA, CA, A10 BA BA, A10 ROW ACTIVATING BA, CA, A10 BA BA, A10 WRITE RE COVERING BA, CA, A10 BA BA, A10 DDR SDRAM (Rev.1.1) Integrated Silicon Solution, Inc. Rev. B 10/31/08 ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address REFRESHING MODE REGISTER SETTING ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B FUNCTION TRUTH TABLE for CKE Current State CKE n-1 CKE SELF- REFRESHING POWER DOWN ALL BANKS IDLE ANY STATE other than listed H L above ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I SIMPLIFIED STATE DIAGRAM POWER APPLIED POWER PREA ON MODE REGISTER SET WRITE 14 DDR SDRAM (Rev.1.1) 256M Double Data Rate Synchronous DRAM PRE CHARGE ALL REFS MRS MRS REFA IDLE CKEH Active ACT Power Down CKEL CKEH ROW ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or multifunctioning. 1. Apply VDD before or the same time as VDDQ 2. Apply VDDQ before or at the same time as VTT & Vref 3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL 4 ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I EXTENDED MODE REGISTER DLL disable / enable mode can be programmed by setting the extended mode register (EMRS). The extended mode register stores these data until the next EMRS command, which may be issued when all banks are in idle state. After tMRD from a EMRS command, the DDR SDRAM is ready for new command ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B /CLK CLK Read Command Address Y DQS DQ CL= 2 /CAS BL= 4 Latency Initial Address Integrated Silicon Solution, Inc. Rev. B DDR SDRAM (Rev.1.1) 10/31/08 256M Double Data Rate Synchronous DRAM Burst Length Column Addressing Sequential Zentel Electronics Corporation A3S56D30/40ETP ...

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... IS43R83200B IS43R16160B, IC43R16160B ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vdd Supply Voltage VddQ Supply Voltage for Output VI Input Voltage VO Output Voltage IO Output Current Pd Power Dissipation Topr Operating Temperature Tstg Storage Temperature DC OPERATING CONDITIONS o (Ta unless otherwise noted) Parameter Supply Voltage Supply Voltage for Output ...

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... IS43R83200B IS43R16160B, IC43R16160B AVERAGE SUPPLY CURRENT from Vdd (Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted) Parameter/Test Conditions Symbol OPERATING CURRENT: One Bank; Active-Read-Precharge;Burst = 2; t IDD1 MIN MIN; IOUT= 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I AC TIMING REQUIREMENTS Symbol AC Characteristics Parameter tAC DQ Output access time from CLK//CLK tDQSCK DQS Output access time from CLK//CLK tCH CLK High level width tCL CLK Low level width tCK CLK cycle time tDS ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B AC TIMING REQUIREMENTS(Continues) Symbol AC Characteristics Parameter tRAS Row Active time tRC Row Cycle time(operation) tRFC Auto Ref. to Active/Auto Ref. command period tRCD Row to Column Delay tRP Row Precharge time tRRD Act to Act Delay time tWR Write Recovery time ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I Notes 1. All voltages referenced to Vss. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified timing and IDD tests may use a VIL to VIH swing 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions ...

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... IS43R83200B IS43R16160B, IC43R16160B Read Operation /CLK CLK Cmd & Add. tRPRE DQS DQ Write Operation / tDQSS=max. /CLK CLK tDQSS tWPRES DQS tWPRE DQ Write Operation / tDQSS=min. /CLK CLK tDQSS DQS tWPRES tWPRE DQ Integrated Silicon Solution, Inc. Rev. B 10/31/08 tCK tCH tDQSCK tQH tAC ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I OPERATIONAL DESCRIPTION BANK ACTIVATE The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row address A0-12. The minimum activation interval between one bank and the other bank is tRRD. ...

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... IS43R83200B Preliminary IS43R16160B, IC43R16160B Preliminary READ After tRCD from the bank activation, a READ command can be issued. 1st Output data is available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length is BL. The start address is specified by A0-9(x8)/A0-8(x16), and the address sequence of burst data is defined by the Burst Type ...

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... IS43R83200B IS43R16160B, IC43R16160B READ with Auto-Precharge (BL=8, CL=2,2.5,3. /CLK CLK Command ACT tRCD Xa A0-9,11,12 Xa A10 BA0,1 00 DQS CL=2 DQ DQS CL=2.5 DQ DQS CL=3 BL/2 + tRP READ BL/2 tRP Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa0 ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst Length is BL. The start address is specified by A0-9(x8)/A0-8(x16), and the address sequence of burst data is defined by the Burst Type ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B /CLK CLK ACT Command tRC Xa A0-9,11, A10 00 BA0,1 DQS DQ 28 DDR SDRAM (Rev.1.1) 256M Double Data Rate Synchronous DRAM WRITE with Auto-Precharge (BL= WRITE Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Zentel Electronics Corporation A3S56D30/40ETP ACT ...

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... Preliminary Preliminary IS43R83200B IS43R16160B, IC43R16160B BURST INTERRUPTION [Read Interrupted by Read] Burst read operation can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1CLK. /CLK CLK Command READ READ Yi Yj A0-9,11, A10 00 00 BA0,1 DQS DQ [Read Interrupted by precharge] Burst read operation can be interrupted by precharge of the same bank ...

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... IS43R83200B I IS43R16160B, IC43R16160B /CLK CLK Command DQS DQ Command DQS CL=2.5 DQ Command DQS DQ /CLK CLK Command DQS DQ Command DQS CL=3.0 DQ Command DQS DQ DDR SDRAM (Rev.1.1) 30 256M Double Data Rate Synchronous DRAM Read Interrupted by Precharge (BL=8) READ PRE READ PRE READ PRE Q0 Q1 ...

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... Preliminary IS43R83200B Preliminary IS43R16160B, IC43R16160B [Read Interrupted by Burst Stop] Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency result, READ to TERM interval determines valid data length to be output. The figure below shows examples of BL=8 ...

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... IS43R83200B IS43R16160B, IC43R16160B Command Command CL=3.0 Command [Read Interrupted by Write with TERM] Command CL=2.0 Command CL=2.5 Command CL=3.0 32 Read Interrupted by TERM (BL=8) /CLK CLK READ TERM DQS DQ READ TERM DQS DQ READ TERM DQS DQ Read Interrupted by TERM (BL=8) /CLK CLK READ TERM ...

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... IS43R83200B IS43R16160B, IC43R16160B [Write interrupted by Write] Burst write operation can be interrupted by write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. /CLK CLK Command WRITE WRITE A0-9,11, A10 0 0 BA0 DQS DQ Dai1 Dai0 [Write interrupted by Read] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data the interrupting READ cycle is " ...

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... IS43R83200B I Preliminary Preliminary IS43R16160B, IC43R16160B I [Write interrupted by Precharge] Burst write operation can be interrupted by precharge of the same or all bank. Random column access is allowed. tWR is referenced from the first positive CLK edge after the last data input. Write Interrupted by Precharge (BL=8, CL=2.5) /CLK ...

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... IS43R83200B Preliminary Preliminary IS43R16160B, IC43R16160B [Initialize and Mode Register sets] /CLK CLK CKE Command NOP PRE A0-12 A10 1 BA0,1 DQS DQ Extended Mode Register Set [AUTO REFRESH] Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbits memory cells ...

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... IS43R83200B IS43R16160B, IC43R16160B [SELF REFRESH] Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once the self-refresh is initiated maintained as long as CKE is kept low. During the self- refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved ...

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... IS43R83200B IS43R16160B, IC43R16160B [Power DOWN] The purpose of CLK suspend is power down. CKE is synchronous input except during the self- refresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT required in the condition of the stable CLK operation during the power down mode. ...

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... IC43R16160B-6BL 133 MHz 7.5 IS43R83200B-75TL 133 MHz 7.5 IS43R16160B-75TL Industrial Range: -40°C to +85°C Frequency Speed (ns) Order Part No. 200 MHz 5 IS43R83200B-5TLI 200 MHz 5 IS43R16160B-5TLI 200 MHz 5 IS43R16160B-5BLI 166 MHz 6 IS43R83200B-6TLI 166 MHz 6 IS43R16160B-6TLI 166 MHz 6 IS43R16160B-6BLI 133 MHz 7.5 IS43R83200B-75TLI 133 MHz 7 ...

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... IS43R83200B IS43R16160B, IC43R16160B Plastic TSOP 66-pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Min Ref. Std. 66 No. Leads (N) A — 1.20 — A1 0.05 0.15 0.002 0.006 A2 — — — b 0.24 0.40 0.009 0.016 C 0.12 0.21 0.005 0.0083 D 22.02 22.42 ...

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... IS43R83200B IS43R16160B, IC43R16160B 60 Ball FBGA (8.0mm x 13.0mm) 40 Integrated Silicon Solution, Inc. Rev. B 10/31/08 ...