IS43R16160B-5TL ISSI, Integrated Silicon Solution Inc, IS43R16160B-5TL Datasheet - Page 15

• Manufacturer Part Number: IS43R16160B-5TL
• Description: IC DDR SDRAM 256MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS43R16160B-5TL

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 200 MHz
• Access Time: 0.7 ns
• Supply Voltage (max): 2.7 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Current: 290 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 706-1085; IS43R16160B-5TL

IS43R83200B
IS43R16160B, IC43R16160B
Integrated Silicon Solution, Inc.
Rev. B
DDR SDRAM (Rev.1.1)
10/31/08
POWER ON SEQUENCE
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the DDR SDRAM is idle state and ready for normal operation.
MODE REGISTER
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when all banks are in idle state. After tMRD from a
MRS command, the DDR SDRAM is ready for new command.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Before starting normal operation, the following power on sequence is necessary to prevent a
Burst Length, Burst Type and /CAS Latency can be
0
DLL Reset
0
0
Latency
Mode
0
0
1
0
Preliminary
Preliminary
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CL
0
DR
YES
NO
/CAS Latency
0
2.5
R
R
R
R
R
2
3
LTMODE
256M Double Data Rate Synchronous DRAM
BT
Length
Burst
Burst Type
BL
Zentel Electronics Corporation
R: Reserved for Future Use
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
A3S56D30/40ETP
A12-A0
CLK
/CLK
/CS
/RAS
/CAS
/WE
BA0
BA1
0
1
BT=0
R
R
R
R
R
2
4
8
Interleaved
Sequential
V
BT=1
R
R
R
R
R
2
4
8
15