IS43R16160B-5TL ISSI, Integrated Silicon Solution Inc, IS43R16160B-5TL Datasheet - Page 24

• Manufacturer Part Number: IS43R16160B-5TL
• Description: IC DDR SDRAM 256MBIT 66TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS43R16160B-5TL

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 200 MHz
• Access Time: 0.7 ns
• Supply Voltage (max): 2.7 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Current: 290 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 706-1085; IS43R16160B-5TL

IS43R83200B
IS43R16160B, IC43R16160B
24
DDR SDRAM (Rev.1.1)
I
I
OPERATIONAL DESCRIPTION
BANK ACTIVATE
the bank addresses (BA0,1). A row is indicated by the row address A0-12. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command to the same bank can be issued.
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the
Command
A0-9,11,12
A precharge command can be issued at BL/2 from a read command without data loss.
BA0,1
/CLK
DQS
CLK
A10
DQ
Preliminary
Preliminary
2 ACT command / tRCmin
ACT
Xa
Xa
00
tRRD
Bank Activation and Precharge All (BL=8, CL=2)
tRCD
ACT
01
Xb
Xb
READ
Y
0
00
tRCmin
256M Double Data Rate Synchronous DRAM
BL/2
tRAS
Qa0
Qa1
Qa2
Precharge all
Qa3
PRE
1
Qa4
Zentel Electronics Corporation
Qa5
tRP
Qa6
A3S56D30/40ETP
Integrated Silicon Solution, Inc.
Qa7
ACT
Xb
Xb
01
10/31/08
Rev. B