M48Z35-70PC1 STMicroelectronics, M48Z35-70PC1 Datasheet - Page 11

• Manufacturer Part Number: M48Z35-70PC1
• Description: IC NVSRAM 256KBIT 70NS 28DIP
• Manufacturer: STMicroelectronics

Specifications of M48Z35-70PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Data Bus Width: 8 bit
• Organization: 32 Kb x 8
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Operating Current: 50 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2879-5

M48Z35, M48Z35Y
Table 4.
1. Valid for ambient operating temperature: T
2. C
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
t
t
WHQX
WLQZ
Symbol
L
t
t
t
t
t
t
t
t
t
t
t
t
t
WLWH
WHAX
DVWH
WHDX
AVWH
AVWL
EHAX
DVEH
EHDX
AVEH
ELEH
= 5 pF (see
AVAV
AVEL
(2)(3)
(2)(3)
WRITE mode AC characteristics
Data retention mode
With valid V
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
into the deselect window during the time the device is sampling V
of the power supply lines is recommended.
When V
preserves data. The internal button cell will maintain data in the M48Z35/Y for an
accumulated period of at least 10 years (at 25°C) when V
As system power returns and V
power supply is switched to external V
V
V
For more information on battery storage life refer to the application note AN1012.
PFD
PFD
Figure 10 on page
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
(min) plus t
(max).
CC
drops below V
CC
applied, the M48Z35/Y operates as a conventional BYTEWIDE™ static
F
REC
. The M48Z35/Y may respond to transient noise spikes on V
15).
(min). Normal RAM operation can resume t
CC
A
Parameter
SO
= 0 to 70 °C; V
falls within the V
, the control circuit switches power to the internal battery which
Doc ID 2608 Rev 9
CC
rises above V
(1)
CC
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
. Write protection continues until V
PFD
(max), V
SO
, the battery is disconnected, and the
PFD
CC
(min) window. All outputs
is less than V
REC
Min
70
50
55
30
30
60
60
0
0
0
0
5
5
5
CC
M48Z35/Y
. Therefore, decoupling
after V
–70
Operating modes
SO
PFD
CC
Max
CC
25
.
CC
exceeds
(min), the
reaches
CC
that reach
fall time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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