M48Z35-70PC1 STMicroelectronics, M48Z35-70PC1 Datasheet - Page 8

• Manufacturer Part Number: M48Z35-70PC1
• Description: IC NVSRAM 256KBIT 70NS 28DIP
• Manufacturer: STMicroelectronics

Specifications of M48Z35-70PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Data Bus Width: 8 bit
• Organization: 32 Kb x 8
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Operating Current: 50 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2879-5

Operating modes
2
Note:
2.1
8/24
Operating modes
The M48Z35/Y also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately 3 V, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2.
1. See
X = V
READ mode
The M48Z35/Y is in the READ mode whenever W (WRITE enable) is high, E (chip enable) is
low. The device architecture allows ripple-through access of data from eight of 264,144
locations in the static storage array. Thus, the unique address specified by the 15 address
inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the data I/O pins within address access time (t
signal is stable, providing that the E and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the chip enable
access time (t
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 6 on page 12
or V
V
IL
Operating modes
SO
; V
ELQV
4.75 to 5.5 V
4.5 to 5.5 V
to V
SO
AVQV
≤ V
) or output enable access time (t
V
PFD
= Battery backup switchover voltage.
or
SO
CC
, the data lines will be driven to an indeterminate state until t
(1)
for details.
(min)
AXQX
(1)
Doc ID 2608 Rev 9
) but will go indeterminate until the next address access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
GLQV
W
X
X
X
IH
IH
IL
).
AVQV
DQ0-DQ7
High Z
High Z
High Z
High Z
CC
D
D
OUT
IN
) after the last address input
. As V
CC
Battery backup mode
CC
M48Z35, M48Z35Y
falls below
CMOS standby
is out of
Standby
Power
Active
Active
Active
AVQV
. If