ST72T331N2T6 STMicroelectronics, ST72T331N2T6 Datasheet - Page 47

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ST72T331N2T6

Manufacturer Part Number
ST72T331N2T6
Description
8-bit Microcontrollers - MCU OTP EPROM 8K SPI/SCI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72T331N2T6

Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
ST7
Data Bus Width
8 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
8 KB
Data Ram Size
384 B
On-chip Adc
Yes
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
8 bit
A/d Channels Available
8
Interface Type
SCI, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
44
Number Of Timers
2
On-chip Dac
No
Program Memory Type
EPROM
Factory Pack Quantity
90
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.5 V
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OC i HR reg-
2. If the OC i E bit is not set, the OCMP i pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 32. Output Compare Block Diagram
16-bit
ister, the output compare function is inhibited
until the OC i LR register is also written.
general I/O port and the OLVL i bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMP i are set while the counter value equals
the OC i R register value (see
behaviour is the same in OPM or PWM mode.
When the timer clock is f
external clock mode, OCF i and OCMP i are set
while the counter value equals the OC i R regis-
ter value plus 1 (see
for generating external events on the OCMP i
pins even if the input capture mode is also
used.
OLV i bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure
CPU
9).
i
R register and the
CPU
/4, f
Figure
/2, OCF i and
OC1E
CPU
OCIE
OC2E
OCF1
8). This
/8 or in
FOLV2 FOLV1
Forced Compare Output capability
When the FOLV i bit is set by software, the OLVL i
bit is copied to the OCMP i pin. The OLV i bit has to
be toggled in order to toggle the OCMP i pin when
it is enabled (OC i E bit=1). The OCF i bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVL i bits have no effect in either One-Pulse
mode or PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
ST72E331 ST72T331
Latch
Latch
1
2
OCMP1
OCMP2
Pin
Pin
47/107
47

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